Displaying 20 results from an estimated 5000 matches similar to: "[LLVMdev] Tail call optimization thoughts"
2007 Aug 11
1
[LLVMdev] Tail call optimization deeds
Okay so i implemented an(other :) initial version for X86-32 backend,
this time based on TOT:
It is not very generic at the moment. Only functions with
callingconv::fastcc and the tail call attribute will be optimized.
Maybe the next step should be to integrate the code into the other
calling convention lowering. Here is what i have at the moment:
If callingconv::fastcc is used the
2007 Aug 13
0
[LLVMdev] Tail call optimization deeds
Hi Arnold and Anton,
Sorry I have been ignoring your emails on this topic. It's an
important task and I really need sometime to think about it (and talk
to Chris about it!) But this has been an especially hectic week. I am
also going to vacation soon so I am not sure when I would get around
to it.
If Chris has time, I am sure he has lots to say on this topic. :-)
Otherwise, please
2007 Sep 06
2
[LLVMdev] RFC: Tail call optimization X86
Hi Evan,
first off thanks to you and Chris for taking time.
On 6 Sep 2007, at 00:57, Evan Cheng wrote:
> We'd like to see tail call optimization to be similar to the target
> independent lowering of ISD::CALL nodes. These are auto-generated
> from ???CallingConv.td files. Some target specific details such as
> function address register (ECX in your example) should be coded in
2007 Sep 11
0
[LLVMdev] RFC: Tail call optimization X86
Hi Arnold,
Thanks for the patch. Some questions and commons:
1. Have you test it against the llvm test suite? Does it work if fp
elimination optimization is turned off?
2. Please follow llvm coding convention and make sure every line fits
in 80 columns.
3.
enum NameDecorationStyle {
None,
StdCall,
- FastCall
+ FastCall,
+ FastCC // the normal fastcc calling convention
};
Why is
2007 Aug 09
1
[LLVMdev] Tail call optimization thoughts
Implementing tail call opt could look like the following:
0.)a fast calling convention (maybe use the current
CallingConv::Fast, or create a CallingConv::TailCall)
1.) lowering of formal arguments
like for example x86_LowerCCCArguments in stdcall mode
we need to make sure that later mentioned CALL_CLOBBERED_REG is
not used (remove it from available
registers in callingconvention for
2007 Sep 23
2
[LLVMdev] RFC: Tail call optimization X86
The patch is against revision 42247.
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2007 Sep 24
2
[LLVMdev] RFC: Tail call optimization X86
On 24 Sep 2007, at 09:18, Evan Cheng wrote:
> +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -info-
> output-file - | grep asm-printer | grep 9
> +; change preceeding line form ... | grep 8 to ..| grep 9 since
> +; with new fastcc has std call semantics causing a stack adjustment
> +; after the function call
>
> Not sure if I understand this. Can you illustrate
2007 Sep 24
0
[LLVMdev] RFC: Tail call optimization X86
Hi Arnold,
This is a very good first step! Thanks! Comments below.
Evan
Index: test/CodeGen/X86/constant-pool-remat-0.ll
===================================================================
--- test/CodeGen/X86/constant-pool-remat-0.ll (revision 42247)
+++ test/CodeGen/X86/constant-pool-remat-0.ll (working copy)
@@ -1,8 +1,10 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep LCPI | count 3
;
2013 Feb 14
2
[LLVMdev] Question about fastcc assumptions and seemingly superfluous %esp updates
Hello,
While investigating one of the existing tests
(test/CodeGen/X86/tailcallpic2.ll), I ran into IR that produces some
interesting code. The IR is very straightforward:
define protected fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
entry:
ret i32 %a3
}
define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
entry:
%tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32
2013 Feb 15
0
[LLVMdev] Question about fastcc assumptions and seemingly superfluous %esp updates
Hey Eli,
On Thu, Feb 14, 2013 at 5:45 PM, Eli Bendersky <eliben at google.com> wrote:
> Hello,
>
> While investigating one of the existing tests
> (test/CodeGen/X86/tailcallpic2.ll), I ran into IR that produces some
> interesting code. The IR is very straightforward:
>
> define protected fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32
> %a4) {
> entry:
>
2013 Feb 15
2
[LLVMdev] Question about fastcc assumptions and seemingly superfluous %esp updates
>> While investigating one of the existing tests
>> (test/CodeGen/X86/tailcallpic2.ll), I ran into IR that produces some
>> interesting code. The IR is very straightforward:
>>
>> define protected fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32
>> %a4) {
>> entry:
>> ret i32 %a3
>> }
>>
>> define fastcc i32 @tailcaller(i32
2013 Feb 15
1
[LLVMdev] Question about fastcc assumptions and seemingly superfluous %esp updates
Hi Arnold,
Thanks for the insights. My comments below:
On Thu, Feb 14, 2013 at 5:30 PM, Arnold Schwaighofer
<aschwaighofer at apple.com> wrote:
> When you enable -tailcallopt you get support for tail calls between functions with arbitrary stack space requirements. That means the calling convention has to change slightly. E.g the callee is responsible for removing it's arguments of
2007 Oct 04
3
[LLVMdev] RFC: Tail call optimization X86
Comments:
CheckDAGForTailCallsAndFixThem -
1.
for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
+ BI = prior(DAG.allnodes_end()); BI != BE; BI--) {
Please use pre-decrement instead of post-decrement.
2. The function is slower than it should be. You are scanning all the
nodes in the DAG twice. You should just examine DAG.getRoot() to make
determine whether it's a
2013 Feb 15
0
[LLVMdev] Question about fastcc assumptions and seemingly superfluous %esp updates
When you enable -tailcallopt you get support for tail calls between functions with arbitrary stack space requirements. That means the calling convention has to change slightly. E.g the callee is responsible for removing it's arguments of the stack. The caller cannot transitively know the tail callee's tailcallee's requirement. Also care must be taken to make sure the stack stays
2007 Sep 11
2
[LLVMdev] RFC: Tail call optimization X86
Begin forwarded message:
> From: Evan Cheng <evan.cheng at apple.com>
> Date: 11 September 2007 19:26:39 GMT+02:00
> To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu>
> Subject: Re: [LLVMdev] RFC: Tail call optimization X86
> Reply-To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu>
>
> Hi Arnold,
>
> Thanks for the patch. Some questions
2007 Aug 08
2
[LLVMdev] Destination register needs to be valid after callee saved register restore when tail calling
Hello, Arnold.
> with the sentence i tried to express the question whether there is a
> way to persuade the code generator to use another register to load (or
> move) the function pointer to (right before the callee saved register
> restore) but thinking a little further that's nonsense.
Why don't define some special op for callee address and custom lower it?
I really
2007 Dec 25
3
[LLVMdev] Optimization feasibility
On 25 Dec 2007, at 03:29, Gordon Henriksen wrote:
> Hi Jo,
>
> On 2007-12-24, at 14:43, Joachim Durchholz wrote:
>
>> I'm in a very preliminary phase of a language project which requires
>> some specific optimizations to be reasonably efficient.
>>
>> LLVM already looks very good; I'd just like to know whether I can
>> push these optimizations
2007 Sep 24
0
[LLVMdev] RFC: Tail call optimization X86
On Sep 24, 2007, at 2:25 AM, Arnold Schwaighofer wrote:
>
> On 24 Sep 2007, at 09:18, Evan Cheng wrote:
>> +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -info-
>> output-file - | grep asm-printer | grep 9
>> +; change preceeding line form ... | grep 8 to ..| grep 9 since
>> +; with new fastcc has std call semantics causing a stack adjustment
>>
2007 Dec 25
0
[LLVMdev] Optimization feasibility
Hi Jo,
On 2007-12-24, at 14:43, Joachim Durchholz wrote:
> I'm in a very preliminary phase of a language project which requires
> some specific optimizations to be reasonably efficient.
>
> LLVM already looks very good; I'd just like to know whether I can
> push these optimizations through LLVM to the JIT phase (which, as
> far as I understand the docs, is a
2016 Jun 26
3
Tail call optimization is getting affected due to local function related optimization with IPRA
According to this http://llvm.org/docs/CodeGenerator.html#tail-call-section,
it seems that adding a new CC for the purpose of local function
optimization seems a good idea because tail call optimization only takes
place when both caller and callee have fastcc or GHC or HiPE calling
convention.
-Vivek
On Sun, Jun 26, 2016 at 1:26 AM, vivek pandya <vivekvpandya at gmail.com>
wrote:
>