similar to: [LLVMdev] SSE levels & x86 code-gen

Hi, We would like to extend the vector operations in llvm a bit. We're hoping to get some feedback on the right way to go, or some starting points. I had previously had some discussion on this list about a subset of the changes we have in mind. All of these changes are intended to make target-independent IR (i.e. IR without machine specific intrinsics) generate better code or be

Erik de Castro Lopo wrote: >> part 1: fixes >> >> part 2: new code >> >> Any comments? > > Applied cpu_part2.patch. Thanks! Thanks. I hope that this code will help to avoid "bug" reports such as http://sourceforge.net/p/flac/bugs/409/ (it seems that the author of this report compiled FLAC without --enable-sse option). OTOH, SSE support is

On Jul 1, 2011, at 2:43 PM, Alistair Lynn wrote: > Hi Andrew- > >> fatal error: error in backend: SSE2 register return with SSE2 disabled > > Is this for 32-bit or 64-bit x86? 64-bit x86. > If it's the latter, the ABI demands > that the return value in this case is in xmm0 - SSE is required. > Well -no-sse -mno-mmx works for EFI as it is pre-boot firmware and

Hello, I want to disable LLVM to use any SIMD registers like sse and avx. I tried -mno-sse and -mno-avx on my Core i7 machine. It seems that the generated assembly still uses xmm registers. Is there any way for LLVM to only use scalar registers? Thanks, Zhi -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, LLVM made a change a few months ago and starting erroring out when a float is returned in x64 and SSE is disabled. This makes sense, really, since it's specified by the ABI that the return value must be put in a register you were told to disable, but it's breaking soft floats in Rust on x64. It seems there are two options: LLVM could break the ABI spec and have working soft floats on

Hi, I''ve a quad-core x86_64 machine (Intel Xeon), with sse/mmx support. However, I want to disable sse/mmx support from HVM guests. How can I do this? Also, is it reasonable to expect illegal instruction fault in non-root VMX mode if a guest VM runs an application with sse/mmx instructions? Thanks, Ashish _______________________________________________ Xen-devel mailing list

Hi, When setting -mattr option on X86, I would like to treat MMX separately from SSE levels. This would allow a client who sets the attributes directly to set the SSE level independent of MMX, e.g., llc -march=x86 -mattr=sse41, one would get sse4.1 with mmx disabled while llc -march=x86 -mattr=mmx -mattr=sse42 will get mmx and sse42. If anyone objects to this change, please let me

Hi Andrew- > fatal error: error in backend: SSE2 register return with SSE2 disabled Is this for 32-bit or 64-bit x86? If it's the latter, the ABI demands that the return value in this case is in xmm0 - SSE is required. Alistair

1. A program can use SSE instructions only if both CPU and OS support SSE. Currently libFLAC tests both CPU and OS for this support, but is it really necessary? Maybe CPU check is enough? Operating systems that don't support SSE (Win95, WinNT 4.0, Linux kernel 2.2 (iirc), ...) are really outdated now. Removing OS check will greatly simplify src/libFLAC/cpu.c. 2. "configure" build

On Monday 22 June 2009 16:37:41 BGB wrote: > as for what targets support which operations, in the case of SSE, go check > the Intel and AMD64 docs. I was assuming that LLVM's implementations were incomplete. Are they now complete? So anything that a CPU can do and LLVM has bindings for is implemented? -- Dr Jon Harrop, Flying Frog Consultancy Ltd. http://www.ffconsultancy.com/?e

Thanks Kevin for the reply. I got the point now :) On 10 Apr 2015 00:18, "Smith, Kevin B" <kevin.b.smith at intel.com> wrote: > For x86_64 ABI, a minimum feature set of SSE2 is required. > > > > Kevin > > > > *From:* llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On > Behalf Of *suyog sarda > *Sent:* Thursday, April 09,

Does anyone have any LLVM IR examples implementing things using the instructions for SSE, like complex arithmetic or 3D vector-matrix stuff? I'd like to have HLVM use them "under the hood" for some things but I cannot see all of the operations that I was expecting (e.g. dot product) and am not sure what works when (e.g. "Not all targets support all types however."). --

Jean-Marc, >I'm still not sure I get it. On an Athlon XP, I can do something like >"mulps xmm0, xmm1", which means that the xmm registers are indeed >supported. Besides, without the xmm registers, you can't use much of >SSE. In the Atholon XP 2400+ that we have in our QA lab (Win2000 ) if you run that code it generates an Illegal Instruction Error. In addition,

Your clang invocation below works for me, and generates target triple in the llvm IR of i386. And then in the specific options for the functions it generates the following: ; Function Attrs: nounwind define float @foo() #0 { entry: ret float 1.000000e+00 } attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"= "true"

I tried building speex with SSE, and found that it crashes for me here: [This is on RH=8.0]: # libtool gdb ./src/speexenc GNU gdb Red Hat Linux (5.2.1-4) [...] This GDB was configured as "i386-redhat-linux"... (gdb) r --rate 8000 --16bit -n /dev/zero /tmp/foo Starting program: /usr/src/speex-1.1.7/src/.libs/lt-speexenc --rate 8000 --16bit -n /dev/zero /tmp/foo Encoding 8000 Hz audio

I'm working on changing the MMX implementation to use intrinsics in all cases, which should stop various optimization passes from creating MMX instructions that screw up the x87 stack. Right now the MMX instructions are split between X86InstrMMX.td and X86InstrSSE.td, presumably on the historical grounds that some of them weren't introduced until SSE or SSSE3, and require

Jean-Marc, Are you sure that you don't need to add just -msse to enable the intrinsics rather than a full fledged -march=pentium3? I did some playing around and I can get intrinsics code to compile with -march=i686 -msse on linux with that. Check out:

Hi Andrew- > Well -no-sse -mno-mmx works for EFI as it is pre-boot firmware and does not have any floating point C code. We use -no-sse and -mno-mmx code to prevent optimized code gen using these registers for optimizations. Whether it's optimised or not doesn't particularly matter, the x86_64 ABI says that floating-point return values go into SSE registers, so that is where LLVM is

Hi all, Recently some great work has been done to implement vector shifts as described in the language reference, and I'd like to contribute by attempting to match these operations on x86 to MMX and SSE instructions whenever possible. I'm experienced in writing MMX and SSE assembly but I'm unfamiliar with how LLVM performs instruction selection. So every bit of information to

On Fri, Apr 02, 2004 at 12:33:13AM -0500, Jean-Marc Valin wrote: > Do you have any sample code for that? Also, how do you tell autoconf to > append '-msse' without running into problems when CFLAGS is not set (and > usually defaults to -g -O2, but not always). Example patch attached. It only tries if the use passes --enable-sse; testing by target arch as Aron suggested is