similar to: [LLVMdev] LLVM Expansions

> From: "Wilfred L. Guerin" <wilfredguerin at gmail.com> > Subject: [LLVMdev] LLVM Expansions > > It is very relevant that LLVM look into handeling HDL and other binary > and analogue operation modeling capbilities, as well as expand this what is binary? you mean digital right? > Without confirming the true characteristics of the lower structure > types and

perhaps one should ask why a compiler has not compiled itself to binary and requires a 3rd party compiler to exist. Someone please send me lli that works on a pxa270 (which has never been tested?) and make sure it runs in PocketPC(win) so I dont have to wait another 20 hours to compile a damned compiler. On 7/24/07, nkavv at physics.auth.gr <nkavv at physics.auth.gr> wrote: > >

fucking hell, listserv... ---------- Forwarded message ---------- From: "Wilfred L. Guerin" <wilfredguerin at gmail.com> Date: Wed, 25 Jul 2007 10:54:46 -0500 Subject: Re: [LLVMdev] Segment Register Use To: Holger Schurig <hs4233 at mail.mn-solutions.de> I was very much expecting this style of response ;) I believe the following characteristics and class of example should

Just to make sure, what's the goal here? Is the goal 1) to have a fast Opus implementation or are you 2) looking for an interesting FPGA implementation project? If 1), then an FPGA is most likely not necessary since Opus is not computationally expensive. If 2), then it depends on the desired size of the project and the desired quality. The simplest encoder possible is indeed simpler than the

(Is this the right list for libao patches?) The following adds support for a sndio plugin to libao. sndio is OpenBSD's new audio API. diff -uNrp libao-0.8.8.orig/configure.ac libao-0.8.8/configure.ac --- libao-0.8.8.orig/configure.ac Thu May 24 12:51:05 2007 +++ libao-0.8.8/configure.ac Mon Dec 8 16:34:44 2008 @@ -300,6 +300,11 @@ dnl Check for Sun audio AC_CHECK_HEADERS(sys/audioio.h)

I'm not aware of an FPGA implementations yet. You could be the first! An encoder implementation would be much easier, because there are almost no rules about encoders. An encoder is free to behave any way it wants, so you could implement a very small subset of Opus and still have a compliant (and useful) encoder. A decoder implementation would be much harder, because decoders are required

I realize I am one of the few who uses the segment registers (especially CS and DS) on the ia32 chips for example, and a definite few with complete segregation models that rival specialized physical processors... GCC still fails to use these correctly and if your LLVM still depends on either Generic or some of the RTL models they use in various processor definitions, I express concern for

Not only do FPGAs not support recursion, we don’t even support calls! All user code must be inlined into one kernel/component, which is then used to create HDL for the FPGA. Mark From: Bruce Hoult <brucehoult at sifive.com> Sent: December 17, 2018 9:28 AM To: Mendell, Mark P <mark.p.mendell at intel.com> Cc: jjones at prc-hsv.com; LLVM Developers Mailing List <llvm-dev at

Hi, HardCloud (www.hardcloud.org) is an extension to the OpenMP 4.X standard that seeks to ease the task of offloading IP-cores to FPGA accelerators in CPU-FPGA architectures. This is achieved by two new clauses [use] and [module] shown in the example below: #pragma omp target device(HARP | HARPSIM | Catapult) map(to: X) map(from: Y) #pragma omp parallel for use(hrw) module(loopback) check

Good day! I'm creating HDL IP CORE (for using in FPGA) for theora encoder (now only I-frames). I don't undestand one moment. Now i develop such stages: 1. From RBG(byer) to YCbCr converter 2. DCT processing (8x8 pixels blocks) 3. Quantizator of DCT coeff. 4. Zig-Zag of quantized DCT coeff. and now i have uresolved last stage of compression - how i must send 8x8 blocks to huffman

Hi, There: Clang fails to compile 254.gap @ CPU2000int suite. The symptom is that executable fail to run with reference input. The root cause is that the compiler mistakenly optimizes expr "x * y / y" into x where the x*y is blindly flagged with nsw without any analysis. The preproceeded code is excerpted bellow: cat -n integer.i --------------------------------- 2361

This has come up before, and we just added -fwrapv to work around the problem: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110131/115969.html Are you compiling without -fwrapv? Cameron On May 6, 2013, at 4:55 PM, Shuxin Yang <shuxin.llvm at gmail.com> wrote: > Hi, There: > > Clang fails to compile 254.gap @ CPU2000int suite. The symptom is that executable

Hi, I am trying to fit a ordinal GEE model using ordgee {geepack}. In order to check the validity of the function, I specified the correlation structure as independence (i.e. constr = "independence") and compared the result with that using polr {MASS}. Because a GEE model with an independent working correlation structure is equivalent to an ordinary GLM model, we would expect the same

I am a physician examining an NHANES dataset available at the NCHS website: http://www.cdc.gov/nchs/about/major/nhanes/nhanes2005-2006/demo_d.xpt http://www.cdc.gov/nchs/about/major/nhanes/nhanes2005-2006/hdl_d.xpt http://www.cdc.gov/nchs/about/major/nhanes/nhanes2005-2006/tchol_d.xpt Thank you to the R authors and the foreign package authors in particular. Importing from the SAS export

Hi, I'm trying to run Fisher's Exact test on the data below, but I'm not sure how interpret the data shown. Can someone tell me what this is saying? Looking at the numbers it should be that there's no significant difference between the HDL and LDL, but a p-value of 1 seems high. Is the low value in the LDL unbound making the test unstable and should I be using an alternative? Best

Hey! I was wondering if active-HDL (VHDL simulator) will work with WINE 1.0? active-HDL (i regret to say) is only for windows.... :( Thanks :)

Hi, I'm trying to connect an HDL F10 device for a friend living in Brazil to the TDM2400 on his Asterisk server. That device should behave like a normal doorbell and it is if connected to an analog PBX. I connected to the TDM2400 and everything works fine except for one thing: when the called party hangs up his phone, the F10 HDL device does not hang up. I'm not brazilian and not

Le 30. 08. 13 11:59, David Chisnall a écrit : > If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). That's a good idea before I go too far , and I think that MyHDL worths a look too. For Symbolics Processor Designer, I tried

Dear R users: I have a continuous outcome variable and four predictors, two continuous and two dichotomous. i would like to use the lattice plot to create scatter plots for the continuous predictors and boxplots for the dichotomous predictors. with 4 continuous variables, this is what i have been doing: trial = rbind ( cbind ( cimt$ant.mean, cimt$age, 1 ), cbind ( cimt$ant.mean, cimt$sbp, 2 ),