similar to: [LLVMdev] NO-OP

>> I am in need of a no-op instruction: an instruction that does not do >> anything, and has no operands. Does LLVM predefine such an instruction? I >> want to transform the program so that there is no empty basic block. > > You can never have an empty basic block. All BBs must have a TerminatorInst. > I've built a pass to split critical edges of machine

Fernando Magno Quintao Pereira wrote: > I am in need of a no-op instruction: an instruction that does not do > anything, and has no operands. Does LLVM predefine such an instruction? I > want to transform the program so that there is no empty basic block. You can never have an empty basic block. All BBs must have a TerminatorInst. Nick

>> I've built a pass to split critical edges of machine functions, and I have >> to insert new basic blocks. Some of them will have MBB->begin() == >> MBB->end(). > > Ah, machine basic blocks are different. They *are* allowed to be empty. > I would like to build an "insertNoOp" and add it to MRegisterInfo. I would have one for each target. For the

> Why do you want to do this? Empty MBBs are valid, and it's probably > better to have your code handle them. Currently, that is the solution. I have a special treatment for empty basic blocks. I think the code would be more homogeneous if there were no empty basic blocks. > > There is a NOP "instruction" on x86, equivalent to XCHG EAX, EAX. The problem with xchk

On 11/23/07, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > Hi, Sanjiv, > > those passes operate on the whole machine function. Each machine > function contains many basic blocks. If a program has many functions, the > register allocator will be called as many times, i.e it does not do > interprocedural allocation. > > best, > >

Dear guys, I want to coalesce some copies, and I would like to know if there is any method that I can call, like JoinCopy from the old (LLVM 1.9) LiveIntervals class. I found it in SimpleRegisterCoalescing (LLVM 2.1), but I do not want to call this analysis, as I have my own. basically, I can determine that two virtuals do not overlap, and I know that it is safe to join them. In

Hi Florian, we though about using UIUC, like in LLVM. Do you guys know if that could be a problem, given that we are mining the functions from github? > Have you thought about integrating the benchmarks as external tests into LLVM’s test-suite? That would make it very easy to play around with. We did not think about it actually. But we would be happy to do it, if the community accepts

Thanks again. One more question here: Since the regalloc works once per function, do I stil have access to the Call graph? Just saving information between regalloc passes for different functions may not be enough for my case. I will need to maintain the regalloc info of various passes in the call graph order. Anyways thanks for your inputs. I will get back if I need to learn more. Sanjiv On Nov

Hi, again, I think you can do it in the same way that the other allocators have been coded, i.e extend RA, register the pass and so forth. I am not sure about the best way to pass information among a run of RegAlloc to the other, maybe the other guys in the list could suggest something. Yet, you can always dump it into a file, and read it again, everytime it is necessary. Remember that

Dear LLVMers, I need help with one error in my register allocator. I am getting errors when folding instructions for the x86 (it does not happen when I use the PowerPC as target). The problem is that, when I execute something like: mi = mbb->insert(mbb->erase(mi), fmi), where mbb is a MachineBasicBlock, valgrind gives this error message: Address 0x42C62B0 is 24 bytes inside a block

Hey, guys, I am creating some move instructions with MRegisterInfo::copyRegToReg. How do I get a pointer to the instruction that I just created? Is there a way to do something like: // mbb is MachineBasicBlock, reg_info is MRegisterInfo MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); reg_info->copyRegToReg(mbb, iter, dst, src, rc); iter--; (???) MachineInstr *

>> And I have a quite fast algo that I believe is simpler than [Budimlic02] >> and I can share it with you :) > > Do you have a paper on this? I'd be interested in seeing it. > Yes, I have a tech report on this page: http://compilers/fernando/projects/soc/ and I have submitted a paper to SAS, and now I am waiting for the review. The coalescing algorithm is described in

Dear guys, what is the best way to implement a swap of floating point registers in X86? For the integer registers, I am using xchg. Is there a similar instruction for floating point? My function to insert swaps is like: void X86RegisterInfo::swapRegs( MachineBasicBlock & mbb, MachineBasicBlock::iterator mi, unsigned r1, unsigned r2, const TargetRegisterClass

Hey guys, I am trying to speed up some of my LLVM/llc passes. Is there a way to use something like gprof on llc? If not, do you guys know anything that I can use to discover which routines of my passes are taking most of the time? thanks, Fernando

Hi, guys, What is the opcode of the instruction to swap two registers in X86? After updating my LLVM branch, I realized that there is no longer an opcode for xchg with two register operands in X86GenInstrNames.inc. I found only instructions to swap memory and registers: XCHG16rm, XCHG32rm, XCHG64rm and XCHG8rm. I am updating from LLVM 2.1 to current trunk. The names that I was

Dear llvmers, I am trying to insert a move instruction where both source and destination registers are physical registers. How is the code for this? I tried this one here: void PhiDeconstruction_Fer::add_move ( MachineFunction & mf, MachineBasicBlock & mbb, unsigned

> And I have a quite fast algo that I believe is simpler than [Budimlic02] > and I can share it with you :) Do you have a paper on this? I'd be interested in seeing it. -Tanya > > Fernando > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >

Hi guys, I have been using a debugger for my register allocator. The debugger happened to be very useful at catching register assignment errors. I've put the debugger on-line, if anyone who is working with register allocation wants to use. The debugger itself has nothing to do with LLVM, but I've coded a spiller that prints the code in a format that the debugger can read. The

Dear LLVMers, I wish someone could help me to clarify a register allocation question. I will use X86 in this example, but it really does not matter too much. Imagine that I have a virtual v stored in register AL, and I am about to cross a function call, that effectively overwrites AL. Well, I have, say, register ESI free, but as it happens, ESI is bigger than AL. It should be

I'm just starting to dive into llvm, hoping to implement a good graph coloring register allocator. I gather that this has been discussed before. What is the RegAllocGraphColoring.cpp currently in the sources? It seems to be the Fred Chow algorithm but it's not mentioned in the documentation anywhere. Does it work? -Dave