similar to: [LLVMdev] Splitting Legalize?

Displaying 20 results from an estimated 10000 matches similar to: "[LLVMdev] Splitting Legalize?"

2018 Feb 02
1
Vector Splitting for Stackmap Operands
HI All, I am current working with SIMD instruction along with stackmap features. Recently I encountered a problem involving legalizing stackmap. In my stackmap, I record all the live values existing at the callsite. One of the operands in my stackmap is an illegal vector type for arm64 architecture ( *v4f64*) and requires vector splitting in order to legalize the node ( *v2f64*). However, I
2008 Oct 26
0
[LLVMdev] Turning on LegalizeTypes by default
On Oct 26, 2008, at 1:03 AM, Duncan Sands wrote: > Hi all, I plan to turn on the new type legalization infrastructure > "LegalizeTypes" by default tomorrow. This is a redesign/ > reimplementation > of the logic currently in LegalizeDAG that turns (for example) 64 bit > arithmetic on a 32 bit machine into a series of 32 bit operations. > As well > as being a
2007 May 21
1
[LLVMdev] Simplifing the handling of pre-legalize vector nodes
Right now there are special SelectionDAG node kinds for operations on "abstract" vector types (VLOAD, VADD, and all the rest), and a special MVT::Vector ValueType for them. These nodes carry two additional operands, constants which specify the vector length and element type. All of this is only used before legalize; then they are replaced with regular node kinds and value types. It
2015 Jun 28
3
[LLVMdev] Legalizing SelectionDAGs with illegal pointer type
On 27 Jun 2015, at 16:13, escha <escha at apple.com> wrote: > >> >> Hi, >> >> I recently started helping with the LLVM AVR backend [1]. The AVR is an 8 bit core with pointer type i16. That makes pointers illegal in the SelectionDAG. As far as I understand it, it is the backends job to legalize these nodes by using the ReplaceNodeResults/LowerOperation callbacks.
2015 Jun 27
3
[LLVMdev] Legalizing SelectionDAGs with illegal pointer type
Hi, I recently started helping with the LLVM AVR backend [1]. The AVR is an 8 bit core with pointer type i16. That makes pointers illegal in the SelectionDAG. As far as I understand it, it is the backends job to legalize these nodes by using the ReplaceNodeResults/LowerOperation callbacks. Is that about right? I have the feeling that the symbolic nodes carrying pointers, like FrameIndex are
2007 Jun 22
3
[LLVMdev] a possible alternative for pre-legalize extended ValueTypes
After doing a bunch of work for moving pre-legalize extended ValueTypes into a table in SelectionDAG, I may have just found a simpler approach. There are under 32 simple ValueType values, so we only really need 5 bits to represent those. ValueType is already a 32-bit type on most hosts; what if we make use of the remaining 27 bits instead of using an external table? If we can assume that vector
2007 Jun 11
0
[LLVMdev] Status of pre-legalize vector changes
On Mon, 11 Jun 2007, Dan Gohman wrote: > Here's a quick update on where I'm at with the pre-legalize vector changes > I'm working on. I hope to have an updated patch ready to a few days, assuming > I don't get too busy with other projects going on. Here are some of the issues > I've come across so far. Great! I'm going to reorder your email a bit to suit my
2007 Jun 13
1
[LLVMdev] Status of pre-legalize vector changes
On Mon, Jun 11, 2007 at 03:39:40PM -0700, Chris Lattner wrote: > On Mon, 11 Jun 2007, Dan Gohman wrote: > > Also, CopyToReg and CopyFromReg lowering/legalization rely on being able to > > create vector-of-vector types. For example, an <8 x double> vector is bitcasted > > to (effectively) <4 x <2 x double>> for x86, allowing EXTRACT_ELEMENT to pull > >
2007 Jun 11
3
[LLVMdev] Status of pre-legalize vector changes
Hello, Here's a quick update on where I'm at with the pre-legalize vector changes I'm working on. I hope to have an updated patch ready to a few days, assuming I don't get too busy with other projects going on. Here are some of the issues I've come across so far. Putting the table for extended ValueTypes in SelectionDAG seems quite involved. There are a lot of places that use
2007 Jun 22
0
[LLVMdev] a possible alternative for pre-legalize extended ValueTypes
On Jun 22, 2007, at 11:06 AM, Dan Gohman wrote: > After doing a bunch of work for moving pre-legalize extended > ValueTypes > into a table in SelectionDAG, I may have just found a simpler > approach. > > There are under 32 simple ValueType values, so we only really need > 5 bits > to represent those. ValueType is already a 32-bit type on most > hosts; what >
2020 Jan 28
2
Handling node through TargetLowering::LowerOperation vs TargetLowering::ReplaceNodeResults
Thank you Craig for explanation. Could be the same algorithm used for custom legalizing given node in LowerOperation and ReplaceNodeResults in case results and inputs of the node are illegal? Or actually such situation is impossible and for given node either LowerOperation or ReplaceNodeResults can be only called? Przemek wt., 28 sty 2020, 18:48 użytkownik Craig Topper <craig.topper at
2016 Feb 01
2
Question about store with unaligned memory address
Hi Bruce, Thanks for response. I also think it is not good way. Do you have the other ways to legalize it? Thanks, JinGu Kang 2016-02-01 13:11 GMT+00:00 Bruce Hoult <bruce at hoult.org>: > In fact this is a pretty bad legalizing/lowering because you only need to > load and edit for the first and last values in the vector. The other words > are completely replaced and don't
2017 Nov 09
2
[GlobalISel] [X86] unable to legalize instruction
Hi , Currently GobalIsel like FastIsel designed to use fallback to DAGIsel in case of failure. You can use -global-isel-abort=2 option. llc -global-isel -pass-remarks-missed="gisel-*" -global-isel-abort=2 simple_foo.ll Regards, Igor From: S. Bharadwaj Yadavalli [mailto:bharadwajy at gmail.com] Sent: Thursday, November 09, 2017 03:36 To: Aditya Nandakumar <proaditya at
2017 Jul 20
3
Issue with DAG legalization of brcond, setcc, xor
Hi, I am having some issues with how some of the instructions are being legalized. So this is my intial basic block. The area of concern is the last three instructions. I will pick and choose debug output to keep this small. SelectionDAG has 36 nodes: t0: ch = EntryToken t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17
2009 Nov 13
3
[LLVMdev] legalize dag problem
Hi I am running into a legalize dag issue after custom lowering a load. If someone can give me pointers that would be great. I am using llvm 2.6 When custom lowering a load, the following code gets executed. Tmp1 = TLI.LowerOperation(Tmp3, DAG); if (Tmp1.getNode()) { Tmp3 = LegalizeOp(Tmp1); Tmp4 = LegalizeOp(Tmp1.getValue(1)); <----------------- what
2008 May 01
1
Data manipulation for random intercept GLMM
Hello, I am working on some examples of GLMM for my students but I am afraid that my way of preparing a dataframe to pass to lmer will make them think that R is a very difficult and un-natural language. Here is for example a simple data set about approval ratings on two different surveys for a random sample of 1600 individuals. > ## Example: Ratings of prime minister (Agresti, Table 12.1,
2008 Oct 26
6
[LLVMdev] Turning on LegalizeTypes by default
Hi all, I plan to turn on the new type legalization infrastructure "LegalizeTypes" by default tomorrow. This is a redesign/reimplementation of the logic currently in LegalizeDAG that turns (for example) 64 bit arithmetic on a 32 bit machine into a series of 32 bit operations. As well as being a cleaner design, it also supports code generation for arbitrary precision integers such as
2015 Mar 04
2
[LLVMdev] ReduceLoadWidth, DAGCombiner and non 8bit loads/extloads question.
Ahmed, Yes, this is the case, I'm sure many other 'spots' in DAGCombiner use this same check or use a similar check with LegalOperations. It just seems like bad form to have core code that generates an illegal node that legalization cannot seem to handle, unless I'm missing something, which is entirely possible. Potentially we are using the wrong LegalAction, though each I've
2017 Jul 21
4
Issue with DAG legalization of brcond, setcc, xor
But isn't kinda silly that we transform to xor and then we transform it back. What is the advantage in doing so? Also, since we do that method, I now have to introduce setcc patterns for i1 values, instead of being able to just use logical pattern operators like not. -Dilan On Fri, Jul 21, 2017 at 11:00 AM Dilan Manatunga <manatunga at gmail.com> wrote: > For some reason I
2009 Jan 20
0
[LLVMdev] Shouldn't DAGCombine insert legal nodes?
Eli: Legal constants would be all well and good for most platforms. I don't think that CellSPU is alone in its support for i64 constants (in fact, the comment in DAGCombine says that the 64-bit constant is inserted to "avoid a constant pool spill"). In many respects, DAGCombine and operation Legalize are co-routines, not separate passes. -scooter On Jan 20, 2009, at 1:23