similar to: [LLVMdev] llvm, gpu execution environments

On Fri, 18 May 2007, Keith Whitwell wrote: > I'm interested in understanding the extent of the assumptions which llvm > makes about the types of hardware it is capable of targeting. Different pieces of the compiler make different assumptions. In particular, the code generator we ship is good for targetting certain classes of devices, but isn't fully general (it doesn't help

Chris Lattner wrote: > On Fri, 18 May 2007, Keith Whitwell wrote: >> I'm interested in understanding the extent of the assumptions which llvm >> makes about the types of hardware it is capable of targeting. > > Different pieces of the compiler make different assumptions. In > particular, the code generator we ship is good for targetting certain > classes of

On Sat, 19 May 2007, Keith Whitwell wrote: >>> It seems that LLVA and by extension Vector-LLVA assumes that looping and >>> branching control flow can be expressed in terms of a simple "br" branch >>> operation. >> >> LLVA is not a part of LLVM, so I won't answer for it. > > OK, I guess I misunderstood the papers I pulled down - my

Is the source code for llva available esp the linux kernel port. Is there a project page for llva ? Mike On 2/3/06, John Criswell <criswell at cs.uiuc.edu> wrote: > Misha Brukman wrote: > > I don't know the current status of the LLVA project, so I will let the > > current developers chime in. Please send all LLVM and LLVA questions to > > llvmdev at cs.uiuc.edu .

Misha Brukman wrote: > I don't know the current status of the LLVA project, so I will let the > current developers chime in. Please send all LLVM and LLVA questions to > llvmdev at cs.uiuc.edu . My apologies for the late reply. > > ----- Forwarded message from N O S P A M <ti_dak at yahoo.com> ----- > > Date: Tue, 17 Jan 2006 09:47:32 -0800 (PST) > From: N O

I don't know the current status of the LLVA project, so I will let the current developers chime in. Please send all LLVM and LLVA questions to llvmdev at cs.uiuc.edu . ----- Forwarded message from N O S P A M <ti_dak at yahoo.com> ----- Date: Tue, 17 Jan 2006 09:47:32 -0800 (PST) From: N O S P A M <ti_dak at yahoo.com> Subject: LLVA, TAO Intent, Morphun, DualCor Hello I want to

On Apr 3, 2007, at 10:55 AM, Andrew Lenharth wrote: > On 4/2/07, Fabian Scheler <fabian.scheler at gmail.com> wrote: >> Hello everybody, >> >> I'm curious whether there have been any attempts to perform >> performance analysis on the LLVA level. I am interested in the >> derivation of flow-facts (loop bounds etc. - what about the >>

On 4/2/07, Fabian Scheler <fabian.scheler at gmail.com> wrote: > Hello everybody, > > I'm curious whether there have been any attempts to perform > performance analysis on the LLVA level. I am interested in the > derivation of flow-facts (loop bounds etc. - what about the > value-range-propagation pass I read about on this list some time ago) > but even more I am

Hello everybody, I'm curious whether there have been any attempts to perform performance analysis on the LLVA level. I am interested in the derivation of flow-facts (loop bounds etc. - what about the value-range-propagation pass I read about on this list some time ago) but even more I am interested in exec-time modeling (how long does it take to execute a bunch of LLVA instructions on

On 7/19/13 3:20 AM, Herbei Dacian wrote: > > > Hi All, > can anyone tell me where I can find the sources for the llva-emu project? The llva-emu code is extremely old and, as I recall, not very feature-filled. It was also done for a class project (I don't think it was used for the original LLVA publication, and it wasn't used for any of the subsequent LLVA/SVA publications

Let me add to one point that Misha made (just to show I actually read these messages!)... >> >> Any ballpark ideas on when an alpha version could be available? Are we >> talking months or years here? > > First of all, I would like to point out that the goal is *NOT* to > compile Linux > to run natively on your favorite architecture; instead, we aim to > compile

Hello, I'm working on a compiler based on LLVM for a SIMD architecture that supports instruction predication. We would like to implement branching on this architecture using predication. As you know the LLVM-IR doesn't support instruction predication, so I'm not exactly sure on what is the best way to implement it. We came up with some ways to do it in LLVM: - Do not add any

> > LLVA specifically is refering to a research project offshoot of llvm. > > LLVM instructions do not have 1:1 mappings to native instructions > > (sometimes multiple llvm instructions map to fewer native insts, > > sometimes the other way around). > > That's correct, and furthermore, LLVA (now called SVA = Secure > Virtual Architecture) uses essentially the

Hi Marcello, I am sure I've seen some postings on the list concerning architectures that support predicated execution and how to map that to LLVM IR, I'm just not sure anymore when and who was involved :). I have implemented your first suggestion for targets that do not have predicated instructions (where control flow to data flow conversion with explicit maintaining of masks and

I posted this question on the llvm channel on irc. I am new to all of this. And I only found out about LLVA as a result of the irc. And please forgive my erroneous terminology. So let me try this as best I can. I want to know if the code of LLVA/LLVM can be used as a virtual processor in configuring the linux kernel? Maybe you have already encountered this and possibly accomplished it as

On Wed, Nov 12, 2003 at 04:05:20PM -0800, Reid Spencer wrote: > On Wed, 2003-11-12 at 11:45, Vikram Adve wrote: > > > This implies that it is not intended for end-user consumption but > > > more for a proof-of-concept and ongoing research potential. > > > > You're being too modest, Misha --- this is going to be the Linux of > > the future :) > >

Hi All, can anyone tell me where I can find the sources for the llva-emu project? I've tried to contact  Michael Brukman or Brian Gaeke but no reply. thank you for any help, dacian -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130719/94fcf74b/attachment.html>

Dear all: To write a compiler for Microsoft Direct3D shaders from our hardware, I have a program which translates the Direct3D shader assembly to LLVM assembly. I added several intrinsics for this purpose. It's a vector ISA and has some special instructions like: * rcp (reciprocal) * frc (the fractional portion of each input component) * dp4 (dot product) * exp (exponential) * max, min These

On 9/19/13 9:53 AM, Herbei Dacian wrote: > > Hi Konstantin, > good point. > but I my intention is to have something like the llva project. If you want something like the LLVA project for user-space applications, then you basically want to use LLVM as-is. The only things missing are the instructions that replace certain in-line assembly sequences that cannot be represented by

Pertti Kellomäki wrote: > John Criswell kirjoitti: > >> So, let me see if I understand this right: >> >> First, it sounds like you're programming on the bare processor, so your >> I/O instructions are either special processor instructions or volatile >> loads/stores to special memory locations. >> > > Yes. In more detail, instruction