similar to: [LLVMdev] Attending Developers' Meeting

Christopher, Thank you for all the work :-) Regarding the regression testing, it is in our plan to contribute into LLVM. The current state of our project is not in the form that we can do this at this time though, but I'm hoping that we can get some minimal functionality into LLVM before LLVM 2.3 (at most LLVM 2.4) release. Looks like you have also (at least on your local project) taken

Alireza, I have added full support for embedded C address spaces to the LLVM IR (see http://llvm.org/docs/LangRef.html#t_pointer). I have not added any support for the fractional types and their operators, though I think this would simply require adding the necessary intrinsics, which is one of the easier things to add to LLVM. Given that LLVM takes the approach of modeling these kinds

Previously we talked about adding new attributes to function to identify the promotion class. > sign_ext_from_i8, sign_ext_from_i16 > zero_ext_from_i8, zero_ext_from_i16 Aren't these attributes more applicable to return value? of course then the question would be if they are also applicable to parameters too? (because we use same attributes for parameters and return value)? or

On Oct 3, 2007, at 3:21 PM, Alireza.Moshtaghi at microchip.com wrote: > Thank you Evan, > I added the return Type::Int8Ty to the switch statement to get it to > work. > I don't know if this can have other consequences, I haven't yet > verified > if the generated Legalized DAG is correct though. If this works, please submit a patch. Otherwise please submit a bug

Thank you Evan, I added the return Type::Int8Ty to the switch statement to get it to work. I don't know if this can have other consequences, I haven't yet verified if the generated Legalized DAG is correct though. A. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Monday, October 01, 2007 3:23 PM To:

ExpandOp is not called at all. In SelectionDAGLegalize::HandleOp() only the ValueType is considered in the switch statement to decide if it is legal or promote or expand. As I trace back (correct me if I'm wrong) these values are set in TargetLowering::computeRegisterProperties() and it is based on the largest register class (in my case the smallest possible pointer size, 16-bit) So it reduces

On Oct 1, 2007, at 11:33 AM, Alireza.Moshtaghi at microchip.com wrote: > So does that mean that LLVM can't lower automatically to 8-bit values? There is no inherent reason. LLVM should be able to lower to 8-bit values. It's probably a bug somewhere. In TargetLowering.h: bool isTypeLegal(MVT::ValueType VT) const { return !MVT::isExtendedVT(VT) && RegClassForVT[VT] !=

So does that mean that LLVM can't lower automatically to 8-bit values? I tried defining 8-bit pointers in the subtarget using "p:8:8:8" but it asserts at line 566 of TargetData.cpp in the default case of TargetData::getIntPtrType() Is it difficult to add 8-bit support? A. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On

Chris, The reasons for not wanting the code generator to modify alloca to global references are: (1) Variable name is not as easily available in the code generator. (2) I did not want to go behind the back of compiler and change the storage class of a variable in the middle of the way. I felt more comfortable to have the frontend generate the correct information to begin with. But it concerns

On Oct 8, 2007, at 3:15 PM, Alireza.Moshtaghi at microchip.com wrote: > I am trying to verify the generated DAG after converting from llvm to > DAG, however I'm not sure if this is correct or not. > Here is the situation: > In order to get LLVM to lower to 8-bit I have to define only 8-bit > registers and the pointer size also to be 8-bit. > Doing so, the attached DAG is

Thank you Chris, That is great news... So his modifications are in llvm-2.2? How has Christopher tested them? Are there attributes or intrinsics that I can also use? A. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chris Lattner Sent: Tuesday, January 29, 2008 9:23 PM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] C

Evan, The machine is 8 bit, and of course all registers are 8-bit too. Memory access on this machine is a bit different. The memory is banked into banks of 256-byte, and you can select the active bank using a bank select register. All instructions can access the memory with an 8-bit operand, so in that sense the address space can be viewed as 256-byte long. On the other hand, there are three

Any thoughts on this? I would like to get it right before jumping into the nuts and bolts of it.... Thanks ________________________________ From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Alireza.Moshtaghi at microchip.com Sent: Thursday, March 12, 2009 10:39 AM To: llvmdev at cs.uiuc.edu Subject: RE: [LLVMdev] promotion of return value.

Hi Ali, I assume this is primarily for interrupt function handling? If so, I have a few ideas to bounce your direction if you're interested. -j On Aug 6, 2009, at 3:32 PM, Alireza.Moshtaghi at microchip.com wrote: > I need to perform call graph analysis (after all modules are merged) > to > find which function calls which, and depending on the attributes that > each

I am trying to verify the generated DAG after converting from llvm to DAG, however I'm not sure if this is correct or not. Here is the situation: In order to get LLVM to lower to 8-bit I have to define only 8-bit registers and the pointer size also to be 8-bit. Doing so, the attached DAG is generated for a load:i16. I have problem understanding this DAG in two places: 1)As you can see the

I moved my code to 2.1 but still the same. If I make ADD i16 legal, then it goes through, but it has problem expanding it to i8. Should I go ahead and customize it and do the same for all instructions? Or there is a more general thing that I can do? A. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chris Lattner Sent:

On Sep 28, 2007, at 4:53 PM, <Alireza.Moshtaghi at microchip.com> <Alireza.Moshtaghi at microchip.com> wrote: > ExpandOp is not called at all. > In SelectionDAGLegalize::HandleOp() only the ValueType is > considered in > the switch statement to decide if it is legal or promote or expand. > As I trace back (correct me if I'm wrong) these values are set in >

On Jan 29, 2008, at 9:56 AM, <Alireza.Moshtaghi at microchip.com> <Alireza.Moshtaghi at microchip.com > wrote: > Christopher, > It has been a while since we last talked about C embedded extensions > in > LLVM, I was moving back and froth from project to project and didn't > get > a chance to follow up. I was wondering if you have made any changes to >

On Sep 27, 2007, at 4:35 PM, <Alireza.Moshtaghi at microchip.com> <Alireza.Moshtaghi at microchip.com> wrote: > I'm working on version 2.0 > The assertion at line 2380 of LegalizeDAG.cpp fails when it is > trying to > lower the add with i16. > > assertion reads: > assert(MVT::isVector(Node->getValueType(0)) && > "Cannot expand this

Attached please find the gdb backtrace dump and the postscript file of the DAG right before assertion. The red Node is the current Node in LegalizeOp() The only thing that I am customizing before we get here is the FORMAL_ARGUMENTS. At this time I don't really care about the arguments, just want to get some global values working. When I trace the program, it is well passed the legalizing of