similar to: [LLVMdev] Boostrap Failure -- Expected Differences?

Displaying 20 results from an estimated 4000 matches similar to: "[LLVMdev] Boostrap Failure -- Expected Differences?"

2007 Apr 30
0
[LLVMdev] Boostrap Failure -- Expected Differences?
On Apr 27, 2007, at 3:50 PM, David Greene wrote: > The saga continues. > > I've been tracking the interface changes and merging them with > the refactoring work I'm doing. I got as far as building stage3 > of llvm-gcc but the object files from stage2 and stage3 differ: > > > warning: ./cc1-checksum.o differs > warning: ./cc1plus-checksum.o differs > >
2017 Jul 01
2
KNL Assembly Code for Matrix Multiplication
Thank You, It means vmovdqa64 zmm22, zmmword ptr [rip + .LCPI0_0] # zmm22 = [8,9,10,11,12,13,14,15] zmm22 will contain 64 bit constant values which are indexes here zmm22=8, 9, 10, 11, 12,13,14,15. not the values loaded from these locations. and zmm2 contains constant 4000. so, vpmuludq zmm14, zmm10, zmm2 ; will multiply the indexes values with 4000, as for array b the stride is 4000. zmm14=
2015 Dec 17
2
llvm-3.6 MCAsmParser x64 Error "invalid operand for instruction" when msb set
Hello, I am experiencing problems, when trying to assemble these two x86-64 Opcodes "add r64, imm32" "imul r64, r64, imm32" When having the most significant bit set for imm32, for example: "add rax, 0x80000000", "add rax, 0xffffffff", ... "imul rbx, rsi, 0x80000000", "imul rbx, rsi, 0xffffffff", ... The Error Message I receive is the
2013 Jul 19
4
[LLVMdev] SIMD instructions and memory alignment on X86
Hmm, I'm not able to get those .ll files to compile if I disable SSE and I end up with SSE instructions(including sqrtpd) if I don't disable it. On Thu, Jul 18, 2013 at 10:53 PM, Peter Newman <peter at uformia.com> wrote: > Is there something specifically required to enable SSE? If it's not > detected as available (based from the target triple?) then I don't think
2018 Dec 01
2
Where's the optimiser gone? (part 5.c): missed tail calls, and more...
Compile the following functions with "-O3 -target i386-win32" (see <https://godbolt.org/z/exmjWY>): __int64 __fastcall div(__int64 foo, __int64 bar) { return foo / bar; } On the left the generated code; on the right the expected, properly optimised code: push dword ptr [esp + 16] | push dword ptr [esp + 16] | push dword ptr [esp + 16] |
2003 Jul 18
2
create a vector looping over a frame
Hello, I have a data.frame > names(popA) [1] "Year" "Series" "Age" "WM" "WF" "HM" "HF" "BM" [9] "BF" "IM" "IF" "AM" "AF" "Yr" how do i loop over a subset of variables in this frame to create a vector of
2014 Jul 13
2
[LLVMdev] IMUL x86 instruction
Hi, The x86 CPU IMUL instruction has forms such as: IMUL reg EDX:EAX ← EAX ∗ reg reg, EAX and EDX are 32bit registers. How can I represent this sort of instruction in LLVM IR ? It is really a 32bit * 32 bit = 64 bit, but no LLVM IR exists to do that. Or, a similar question: What LLVM IR would produce this IMUL instruction form? For context, I am writing a x86 to LLVM IR decompiler, so wish to
2005 Feb 22
5
[LLVMdev] Area for improvement
I noticed that fourinarow is one of the programs in which LLVM is much slower than GCC, so I decided to take a look and see why that is so. The program has many loops that look like this: #define ROWS 6 #define COLS 7 void init_board(char b[COLS][ROWS+1]) { int i,j; for (i=0;i<COLS;i++) for (j=0;j<ROWS;j++) b[i][j]='.';
2019 Apr 08
2
[GSoC] Supporting Efficiently the Shift-vector Instructions of the Connex Vector Processor
Hello, I am applying for Google Summer of Code with a project related to LLVM and Connex SIMD processor and I would appreciate some feedback on the proposal. The proposal can be found here: https://docs.google.com/document/d/1pBRbW8pU9GV8zWCJQrILhynNEBpGXJKtev1j7ekXfqs/edit?usp=sharing Thank you, Andrei Popa
2004 Nov 12
2
Boot from CD -> system + data on USB storage
Hi, I am looking for a solution to boot MY system on any PC. To store most of the system and all of my data I want to use an USB storage (in my case an external USB harddisk (2.0 capable)). Since booting off an USB device is not an universal thing I would prefer to have a boot disk with a minimal system - just enough to load most (all?) of the system from the attached USB device. Is this an
2005 Feb 22
0
[LLVMdev] Area for improvement
On Mon, 21 Feb 2005, Jeff Cohen wrote: > I noticed that fourinarow is one of the programs in which LLVM is much slower > than GCC, so I decided to take a look and see why that is so. The program > has many loops that look like this: > > #define ROWS 6 > #define COLS 7 > > void init_board(char b[COLS][ROWS+1]) > { > int i,j; > > for
2018 Nov 22
4
[PATCH net 1/2] virtio-net: disable guest csum during XDP set
We don't disable VIRTIO_NET_F_GUEST_CSUM if XDP was set. This means we can receive partial csumed packets with metadata kept in the vnet_hdr. This may have several side effects: - It could be overridden by header adjustment, thus is might be not correct after XDP processing. - There's no way to pass such metadata information through XDP_REDIRECT to another driver. - XDP does not
2018 Nov 22
4
[PATCH net 1/2] virtio-net: disable guest csum during XDP set
We don't disable VIRTIO_NET_F_GUEST_CSUM if XDP was set. This means we can receive partial csumed packets with metadata kept in the vnet_hdr. This may have several side effects: - It could be overridden by header adjustment, thus is might be not correct after XDP processing. - There's no way to pass such metadata information through XDP_REDIRECT to another driver. - XDP does not
2013 Dec 10
3
[LLVMdev] Summary of TableNextGen BOF
Hello everyone. I apologise for the sizeable delay in sending this. The BoF was attended by quite a lot of people and there was general agreement that tablegen needs improvement in some shape of form. However there are many divergent ideas as to how to go about this improvement. Of course this is completely natural, tablegen being a versatile tool used by many different people for many different
2005 Feb 22
2
[LLVMdev] Area for improvement
Sorry, I thought I was running selection dag isel but I screwed up when trying out the really big array. You're right, it does clean it up except for the multiplication. So LoopStrengthReduce is not ready for prime time and doesn't actually get used? I might consider whipping it into shape. Does it still have to handle getelementptr in its full generality? Chris Lattner wrote:
2018 Dec 01
2
Where's the optimiser gone? (part 5.b): missed tail calls, and more...
Compile the following functions with "-O3 -target i386" (see <https://godbolt.org/z/VmKlXL>): long long div(long long foo, long long bar) { return foo / bar; } On the left the generated code; on the right the expected, properly optimised code: div: # @div push ebp | mov ebp, esp | push dword ptr [ebp + 20] | push
2017 Mar 19
1
[PATCH] pxe: Never chain to the original ISR
The behaviour of default ISRs as provided by the BIOS varies wildly between platforms. Some will simply iret, some will send EOI, some will send EOI and disable the interrupt at the PIC, some will crash the machine due to single-bit errors in the ISR address. When PXENV_UNDI_ISR_IN_START returns PXENV_UNDI_ISR_OUT_NOT_OURS, send the EOI ourselves rather than risking the unpredictable behaviour
2007 Apr 27
5
Option valid user not expanded for groups
Hi, I have a AIX 5.3 machine with Samba 3.0.24c joined into one Windows 2003 ADS server OK. I can request basic information, user lookup, domain lookup(wbinfo, id, net groupmap). When I want to acces the share \\node05\brom from one Windows station I receive a popup window password. In the log of the samba for that machine I found: [2007/04/27 10:48:27, 2] auth/auth.c:check_ntlm_password(319)
2013 Apr 08
1
[LLVMdev] [PATCH] Two patches related to ARM TrustZone support
Hi. Please see attached for review two patches related to ARM TrustZone. The first patch (LLVM-705.trustzone.patch) declares a new subtarget feature for TrustZone and adds it as requirement for the Secure Monitor Call instruction. The second patch (LLVM-706.trustzone_cortex.patch) applies the newly created feature to the relevant processors. Regards, Mihai Popa -- IMPORTANT NOTICE: The contents
2004 Jan 20
7
Distribution Diversity at Shorewall.net
Since RedHat announced the discontinuence of RedHat Linux, I''ve been diversifying shorewall.net. The systems here now are as follows: a) Firewall -- Debian testing (Installed using the Sarge online installer). b) File Server -- SuSE 9.0 Professional c) Desktop -- Mandrake 9.0 d) Web/Mail -- RedHat 9.0 I think that I will wait until I can afford to build a new