similar to: [LLVMdev] testing LLVM without llvm-gcc?

Displaying 20 results from an estimated 60000 matches similar to: "[LLVMdev] testing LLVM without llvm-gcc?"

2007 Sep 04
0
[LLVMdev] [PATCH]: Add SparseBitmap implementation
On Tue, Sep 04, 2007 at 10:35:10AM -0400, Daniel Berlin wrote: > On 9/4/07, Dan Gohman <djg at cray.com> wrote: > > On Fri, Aug 31, 2007 at 08:10:33PM -0400, Daniel Berlin wrote: > > > + template <int ElementSize> > > > + class SparseBitmap { > > > > Do you expect clients will often want custom ElementSize values? Otherwise, > > it seems
2006 Dec 19
0
[LLVMdev] alias-aware scheduling
On Dec 19, 2006, at 12:13 PM, Dan Gohman wrote: > Hello, > > I did a little experiment modifying LLVM to be able to use alias- > analysis > information in scheduling so that independent memory operations may be > reordered. I am not sure if it is a good idea to do this at scheduling time. LLVM explicitly models control flows dependencies as chain operands. This eliminated
2006 Dec 20
1
[LLVMdev] alias-aware scheduling
On Tue, Dec 19, 2006 at 01:31:10PM -0800, Evan Cheng wrote: > > On Dec 19, 2006, at 12:13 PM, Dan Gohman wrote: > > > Hello, > > > > I did a little experiment modifying LLVM to be able to use alias- > > analysis > > information in scheduling so that independent memory operations may be > > reordered. > > I am not sure if it is a good idea to
2007 Sep 04
2
[LLVMdev] [PATCH]: Add SparseBitmap implementation
On 9/4/07, Dan Gohman <djg at cray.com> wrote: > On Fri, Aug 31, 2007 at 08:10:33PM -0400, Daniel Berlin wrote: > > Suggestions, criticisms, etc, are welcome. > > I haven't studied the implementation, but I have a few comments on > the interface, and some style comments, below. > > > Index: include/llvm/ADT/SparseBitmap.h > >
2007 Feb 06
1
[LLVMdev] automatically generating intrinsic declarations
On Mon, Feb 05, 2007 at 12:28:56PM -0800, Chris Lattner wrote: > On Mon, 5 Feb 2007, Dan Gohman wrote: > > > LLVM knows what all the types of the intrinsic functions are; I thought, > > why are users (including llvm-gcc...) required to duplicate all this > > information in order to use them? I mean in order to call > > getOrInsertFunction to get declarations for
2007 Jul 12
0
[LLVMdev] Atomic Operation and Synchronization Proposal v2
On Thu, Jul 12, 2007 at 10:06:04AM -0500, David Greene wrote: > On Thursday 12 July 2007 07:23, Torvald Riegel wrote: > > > > The single instruction constraints can, at their most flexible, constrain > > > any set of possible pairings of loads from memory and stores to memory > > > > I'm not sure about this, but can we get issues due to "special"
2007 Feb 12
1
[LLVMdev] using a SCEV
Hello, If I have a value with a SCEV for which the hasComputableLoopEvolution member function returns true for a given loop, is there a way to construct the value one or more iterations ahead in the loop? I guess I can dyn_cast the SCEV down to each of the various subclasses and construct these values myself for each one, but I'm wondering if there's something I missed. Thanks, Dan --
2006 Dec 19
3
[LLVMdev] alias-aware scheduling
Hello, I did a little experiment modifying LLVM to be able to use alias-analysis information in scheduling so that independent memory operations may be reordered. Attached is a patch which implements this. I copied some routines from DAGCombiner.cpp for using SDOperands with alias queries; it should probably be factored out somewhere so the code can be shared. I reorganized
2007 Sep 04
0
[LLVMdev] [PATCH]: Add SparseBitmap implementation
On Fri, Aug 31, 2007 at 08:10:33PM -0400, Daniel Berlin wrote: > Suggestions, criticisms, etc, are welcome. I haven't studied the implementation, but I have a few comments on the interface, and some style comments, below. > Index: include/llvm/ADT/SparseBitmap.h > =================================================================== > --- include/llvm/ADT/SparseBitmap.h (revision
2007 Feb 05
2
[LLVMdev] automatically generating intrinsic declarations
LLVM knows what all the types of the intrinsic functions are; I thought, why are users (including llvm-gcc...) required to duplicate all this information in order to use them? I mean in order to call getOrInsertFunction to get declarations for them. So I wrote this patch, which allows all this code to be generated automatically. Is this a good approach? Dan -- Dan Gohman, Cray Inc. <djg at
2007 Jun 21
0
[LLVMdev] PassManager vs FunctionPassManager
On Jun 21, 2007, at 4:13 PM, Dan Gohman wrote: > Right now, addPassesToEmitFile requires a FunctionPassManager. If I'm > working with code that uses a plain PassManager and want it to > generate > code, are there any options better than doing this: That's what FPPassManager does (include/llvm/PassManagers.h) . Function pass manager itself is a module level pass.
2007 Jun 21
2
[LLVMdev] PassManager vs FunctionPassManager
Right now, addPassesToEmitFile requires a FunctionPassManager. If I'm working with code that uses a plain PassManager and want it to generate code, are there any options better than doing this: /** * Wrapper class to run a FunctionPassManager as a ModulePass so that it * can be added to a plain PassManager. */ class FunctionPassManagerModulePass : public ModulePass { FunctionPassManager
2007 Jun 25
1
[LLVMdev] PassManager vs FunctionPassManager
On Thu, Jun 21, 2007 at 04:37:14PM -0700, Devang Patel wrote: > > On Jun 21, 2007, at 4:13 PM, Dan Gohman wrote: > > > Right now, addPassesToEmitFile requires a FunctionPassManager. If I'm > > working with code that uses a plain PassManager and want it to > > generate > > code, are there any options better than doing this: > > That's what
2007 Jun 18
0
[LLVMdev] alias information on machine instructions
On Fri, Jun 15, 2007 at 04:16:57PM +0200, Florian Brandner wrote: > hi, > > > Florian Brandner wrote: > > Dan Gohman wrote: > >> On Wed, May 23, 2007 at 12:23:38AM -0700, Chris Lattner wrote: > >>> Right. The original Value*'s are preserved in the DAG, but dropped when > >>> MachineInstrs are created. We could add a machineoperand to
2007 Nov 26
2
[LLVMdev] Problem with regression tests using stderr
On Tue, Nov 20, 2007 at 07:01:25PM -0800, Bill Wendling wrote: > I think that it's a hold-over to how things used to be done. IIRC, > you had to have the && at the end of the RUN line if you had another > RUN line that needed to be executed. That's no longer the case, of > course. Thanks. I'll remove the && from the one test that still has it then.
2007 Nov 27
1
[LLVMdev] Problem with regression tests using stderr
Ok, it's PR1826. Dan On Mon, Nov 26, 2007 at 05:15:38PM -0800, Tanya M. Lattner wrote: > > Can you please file a bug for this (i havent seen one yet). > > Thanks, > Tanya > > On Mon, 26 Nov 2007, Dan Gohman wrote: > > > On Tue, Nov 20, 2007 at 07:01:25PM -0800, Bill Wendling wrote: > >> I think that it's a hold-over to how things used to be
2007 Jul 09
1
[LLVMdev] use/def/kill problem in LiveVariables.cpp
In LiveVariables.cpp, when traversing the instructions, all defs of registers are initially marked as kills. See the code around the comment "Defaults to dead". Then later on, when a pass changes instructions, the LiveVariables code updates the kills lists, but it only does so for uses, not defs. See the code around the comment "If this is a kill of the value, update the VI kills
2007 Nov 20
2
[LLVMdev] Problem with regression tests using stderr
I was attempting to write a test that involves grepping though the stderr produced by opt -analyze, but found that my test was passing even before I fixed the bug I was writing the test for! I found that this one-line sure-fail test: ; RUN: echo hi |& false passes. I also tried 2>&1, because I've seen some tests do that, though that doesn't appear to work in this context
2007 Apr 20
3
[LLVMdev] SCEV ordering
The SCEV framework sorts operands of commutative SCEVs by their getSCEVType() value, and then does an ad-hoc sort to group repeated operands, but it does not do a full sort. In some test cases I'm looking at right now, this causes it to miss opportunities to reuse SCEV objects, as in cases like this: ( %i + %r54 + %r59) ( %r54 + %r59 + %i) As a result, passes like LoopStrengthReduce
2007 May 23
2
[LLVMdev] alias information on machine instructions
On Wed, May 23, 2007 at 12:23:38AM -0700, Chris Lattner wrote: > On Fri, 4 May 2007, Florian Brandner wrote: > > i had a look at the SelectionDAG based schedulers. it seems that > > aliasing loads/stores are chained together by the DAGCombiner. after > > scheduling, when the MachineInstrs are created, the alias information > > cannot be used anymore in the current