Displaying 20 results from an estimated 700 matches similar to: "[LLVMdev] using the constant pool during select"
2012 Nov 24
2
[LLVMdev] Fwd: Prevention register promotion at the isel codegen phase
Sorry, forgot to Reply-All.
Begin forwarded message:
> From: Steve Montgomery <stephen.montgomery3 at btinternet.com>
> Subject: Re: [LLVMdev] Prevention register promotion at the isel codegen phase
> Date: 24 November 2012 17:09:58 GMT
> To: Joseph Pusdesris <joe at pusdesris.com>
>
> I had a similar problem trying to implement reg-mem operations. The solution I
2012 Nov 24
0
[LLVMdev] Fwd: Prevention register promotion at the isel codegen phase
Yes, this is very helpful! Thank you!
How does this work when exiting a variable's liveness range? Will it
automatically know to free the stack slot for reuse?
-Joe
On Sat, Nov 24, 2012 at 12:23 PM, Steve Montgomery <
stephen.montgomery3 at btinternet.com> wrote:
> Sorry, forgot to Reply-All.
>
> Begin forwarded message:
>
> *From: *Steve Montgomery
2009 Feb 17
1
[LLVMdev] ARM backend playing with alternative jump table implementations
Hi list:
I have been trying to get my feet wet with the ARM backend.
As a warmup exercise I wanted to be able to move
jumptables especially large ones out of the code section.
Currently the idiom for jump tables loooks like this
// .set PCRELV0, (.LJTI9_0_0-(.LPCRELL0+8))
// .LPCRELL0:
// add r3, pc, #PCRELV0
// ldr pc, [r3, +r0, lsl #2]
// .LJTI9_0_0:
//
2014 Feb 08
2
[LLVMdev] selecting ISD node - help
Hey, I wanted to add an intrinsics to read MSRs.
So I added the intrinsics and lowered it to a new ISD node I created
ISD::RDMSR, its first operand is the MSR id.
I added a case in X86DAGToDAGISel::Select for ISD::RDMSR.
Now I know rdmsr works like so:
mov r/ecx, <id>
rdmsr
r/eax holds the lower 32/64 bit
>From what I understood this needs a Token Factor node, nodes which are
2006 Dec 19
3
[LLVMdev] alias-aware scheduling
Hello,
I did a little experiment modifying LLVM to be able to use alias-analysis
information in scheduling so that independent memory operations may be
reordered.
Attached is a patch which implements this. I copied some routines from
DAGCombiner.cpp for using SDOperands with alias queries; it should
probably be factored out somewhere so the code can be shared. I
reorganized
2012 Dec 02
2
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
Hi, Joseph, I guess getLoad() will either search an existed SDValue
*OR* create a new one for a non-existed one depending on real
parameters.
Since you use exactly the same attributes dupVal/dupNode have, no
doubt getLoad() return the old one.
I am not sure it's *volatile* that let you get a new result, you might
want to try change some other parameters and check what it turns out.
Regards.
2009 Apr 13
1
[LLVMdev] Porting LLVM backend is no fun yet
Dan Gohman wrote:
> There certainly are wishlist items for TableGen and TableGen-based
> instruction descriptions, though I don't know of an official list.
> Offhand,
> a few things that come to mind are the ability to handle nodes with
> multiple results,
Is there an official workaround, BTW?
- Volodya
2012 Dec 02
0
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
So I think I have made some progress.
SDValue dupVal = consumer->getOperand(OpNo);
LoadSDNode *dupNode = (LoadSDNode*) dupVal.getNode();
SDValue newLoad = CurDAG->getLoad(dupVal.getValueType(),
dupVal.getDebugLoc(),
dupVal.getOperand(0), dupVal.getOperand(1),
dupNode->getPointerInfo(),
2012 Dec 02
0
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
Yes, changing parameters will create a new Node, but is there some way I
can force a new node with the same parameters?
-Joe
On Sat, Dec 1, 2012 at 10:57 PM, Triple Yang <triple.yang at gmail.com> wrote:
> Hi, Joseph, I guess getLoad() will either search an existed SDValue
> *OR* create a new one for a non-existed one depending on real
> parameters.
>
> Since you use
2012 Sep 03
1
[LLVMdev] Selection DAG output as bare DAG, code review
Hello all,
I recently foudn myself wanting to view the basic blocks in the
selection DAG as pure DAGs - so just as a list of edges, with no other
information. I added the below code to the start of the "
void SelectionDAGISel::CodeGenAndEmitDAG()" function. It creates a
separate txt file for each basic block and gives a list of edges
between nodes. The segment of code is below -
2012 Dec 02
2
[LLVMdev] Splitting a load with 2 consumers into 2 loads.
Hi, Joe.
I am sorry I did not catch your point. Can you provide more details?
Since SDValue/SDNode can be used multiple times, why would you want to
create two identical objects
instead of reference to the same one?
2012/12/2 Joseph Pusdesris <joe at pusdesris.com>:
> Yes, changing parameters will create a new Node, but is there some way I can
> force a new node with the same
2008 Feb 18
0
[LLVMdev] More address registers
2008/2/15, Andreas Fredriksson <deplinenoise at gmail.com>:
>
> I tried mocking this up using the following. (Base is what's returned as
> the Ax in the move expression above when the DAG is constructed due to
> SelectAddr().)
>
> SDOperand chain = CurDAG->getCopyToReg(Base, M68K::A3, Base);
> Base = CurDAG->getCopyFromReg(chain, M68K::A3, MVT::i32);
2012 Feb 07
3
[LLVMdev] DAG optimization and lowering algorithm
Hi,
I'm trying to build code for very short function and I encounter with a problem (or bug) in DAG selection algotithm.
I have a node that was created in Combine(BeforeLegalizeTypes) and should be optimized in Combine(AfterLegalizeTypes). But LegalizeTypes() did not change anything and Combine(AfterLegalizeTypes) was not called.
Vector legalization that comes afterwards just scalarized the
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
Per subject, this patch adding an additional pass to handle vector
operations; the idea is that this allows removing the code from
LegalizeDAG that handles illegal types, which should be a significant
simplification. There are still some issues with this patch, but does
the approach look sane?
-Eli
-------------- next part --------------
Index: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
2016 Oct 29
1
Problems with Inline ASM expressions generated in the back end
Hello.
I generated in the back end by hand (in C++ code, not with TableGen) some fancy
assembly code using Inline ASM expressions and if I use 2 functions in my source code (but
NOT just 1 function; I will not present the functions, but each requires me to generate an
Inline ASM expression) I get this error at compilation (at scheduling):
BB#0: derived from LLVM BB %entry
2008 Feb 15
2
[LLVMdev] More address registers
Hi again,
I'm finally getting some time to work on my m68k backend again. :)
I was trying to solve the problem that loads from arbitrary addresses need
to go through address registers. 68k allows flexible addressing similar to
what the x86 can do, only that the adressing base has to reside in an
address register:
move.size[b/w/l] <Displacement>(Ax, Dx * Scale[1/2/4/8]), <Dest>
2010 Sep 09
2
[LLVMdev] Possible missed optimization? 2.0
>>Note that the isCommutable flag is only really useful for two-address
instructions. If the two inputs are not constrained, nothing is really won
by swapping them.
Ahh i see, good to know that.
>> Does the -view-*-dags output look correct?
They do look correct, there are three Xmul_lohi blocks, one returns the low
part copied into R14 and the rest of combinations get added and merged
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 5:26 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
>> Can you explain why you chose the approach of using a new pass?
>> I pictured removing LegalizeDAG's type legalization code would
>> mostly consist of finding all the places that use TLI.getTypeAction
2017 Jul 29
2
ISelDAGToDAG breaks node ordering
Hi,
During instruction selection, I have the following code for certain LOAD
instructions:
const LoadSDNode *LD = cast<LoadSDNode>(N);
SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT,
PtrVT, MVT::Other,
LD->getBasePtr(), LD->getChain());
// Honestly, I have no idea what this does, but other memory
// accessing instructions
2012 Feb 07
0
[LLVMdev] DAG optimization and lowering algorithm
On Mon, Feb 6, 2012 at 11:54 PM, Demikhovsky, Elena
<elena.demikhovsky at intel.com> wrote:
> Hi,
>
> I'm trying to build code for very short function and I encounter with a problem (or bug) in DAG selection algotithm.
> I have a node that was created in Combine(BeforeLegalizeTypes) and should be optimized in Combine(AfterLegalizeTypes). But LegalizeTypes() did not change