similar to: [LLVMdev] problems defining the stack layout

On Tue, 15 Aug 2006, [UTF-8] Rafael Esp?ndola wrote: > I am having some problems defining the stack layout on ARM. It should look > like > > Incoming vars > ----------------- > Saved Link Register > ----------------- > Local vars > ----------------- > > The problem is that the the first local variable is being assigned to > the same location as the link

> I'm not familiar with the ARM ISA, so I don't know the right answer. The > OffsetOfLocalArea is used for ISAs (like X86) where the call sequence > modifies the stack pointer (in the case of X86, the call instruction > pushes a 4/8-byte return value). If ARM is like PPC, where the return > address is implicitly copied into a physreg, then you should probably use >

Hi, Target overrides of processFunctionBeforeFrameFinalized() are misused in two cases (MBlaze and PowerPC) to set the offsets of objects. Unfortunately this has no effect because the offsets are immediately reset by calculateFrameObjectOffsets(). The PowerPC backend does this to setup the stack frame layout according to the ABI. Ie. it spills the registers etc. in a fixed layout. How to do

In ARM the stack should be 8 bytes aligned during function calls. A function that has at least one function call then has a stack size of 8 bytes. PEI::calculateFrameObjectOffsets corretly computes this correctly. The problem is that the alignment is computed before adding space for the call frame size. This is done in emitProlog. Currently the ARM backend has a bug in that it doesn't align

> That is irrelevant. The PEI code needs to know how much stack space is > required for each call to allocate and align the stack frame properly. It > gets this info from the ADJCALLSTACK instructions. I see. Looking at PEI::calculateCalleeSavedRegisters shows that the ADJCALLSTACK instructions is used to set up MaxCallFrameSize. Adding debug prints also show that in the example code

Hello, it seems the Prolog/Epilog insertion does not correctly align stack for me. Consider the PEI::calculateFrameObjectOffsets method. It only aligns the stack if FFI->hasCalls() is true. The only place where MachineFrameInfo::setHasCalls is invoked is PEI::saveCallerSavedRegisters and the value 'true' is only passed when there are instructions with opcodes equal

I'm confused as to the logic used in the register scavenger when it cannot find a free register. I would think that it would want to free up the emergency spill slot immediately after it's use, because otherwise there is a chance of needing to use the emergency slot again and not be able to. Instead it tries to restore it only right before register it is freeing up. Maybe I'm

I'm investigating a bug associated with debug information that manifests itself in the XCore backend (PR11105). I'd like to understand what the expected behavior of eliminateFrameIndex() is when it is called on a dbg_value machine instruction. Currently the XCore target replaces the frame index with the frame register and sets the next operand to the byte offset from the frame

Hi Reed, the register scavenger (RS) also keeps track of live registers. This way it "knows" that the register that was spilled/restored far apart is available. Let say you had the following code. You need to find a register to keep vreg1 and vreg2 in. R1 = .... // <- RS current liveness state; we have called RS->forward(It) where It points to here vreg1 = add SP, 1000 ... =

Hello, for an architecture that doesn't have a good way to load/store a given register class to memory, is it instead easy to spill/fill from another register class instead? e.g. - storeRegToStack/loadRegFromStack use a pseudo instruction and add virtual register operand is not supported (spill optimization doesn't seem to like this). - AMDGPU backend seems to do sth. similar? The only

Hi! I'm making a strange observation in my backend, that ends in illegal code: Version 1: - I lower FrameIndex to TargetFrameIndex (nothing special) - I generate a special address-register ADD instruction in eliminateFrameIndex() to write FramePointer + offset into a new address-register - I use explicit load and store and address-registers in my target instruction patterns: eg (store

Hi, right now, LLVM does register spilling by: 1. Creating stack object 2. Passing index of that stack object to MRegisterInfo::storeRegToStackSlot 3. At later stage, frame indices are replaced by calling to MRegisterInfo::eliminateFrameIndex. This works for me, but there's slight problem. The target does not have "register + contant" addressing mode, so accessing frame index

Hi Richard, Thanks for working on this! Your patched solved my initial problem, but introduced another one. Please find attached another BC file that fails on xcore with the linear scan regalloc. This is the error message I get eliminateFrameIndex Frame size too big: -3 0 llc 0x08affd1e 1 libc.so.6 0xb7d35a01 abort + 257 2 llc 0x081a0972

I need to use ‘createVirtualRegister’ for a specific case in my ‘eliminateFrameIndex’ function implementation. However, whenever that code is executed, I get the assertion "MachineCopyPropagation should be run after register allocation!” at a later stage. I have seen that at least a couple of backend implementations (including ARM Thumb) create virtual registers in ‘eliminatedFrameIndex’.

Hello all, For my custom processor backend I am trying add some instruction using BuildMI() inside eliminateFrameIndex(). I tried RegScavenger like this: unsigned RegUnused0 = RS->FindUnusedReg(&LASER::GNPRegsRegClass); if (!RegUnused0) RegUnused0 = RS->scavengeRegister(&LASER::GNPRegsRegClass, II, SPAdj); assert(RegUnused0 && "Register scavenger failed");

On Oct 10, 2011, at 10:26 AM, Richard Osborne wrote: > I'm investigating a bug associated with debug information that manifests > itself in the XCore backend (PR11105). I'd like to understand what the > expected behavior of eliminateFrameIndex() is when it is called on a > dbg_value machine instruction. That is up to the target. The TII::emitFrameIndexDebugValue() hook is

Roman Levenstein wrote: > Hi Richard, > > Thanks for working on this! Your patched solved my initial problem, > but introduced another one. Please find attached another BC file that > fails on xcore with the linear scan regalloc. > > This is the error message I get > eliminateFrameIndex Frame size too big: -3 > 0 llc 0x08affd1e > 1 libc.so.6 0xb7d35a01 abort

On Wednesday, July 21, 2010 11:21 AM, Jakob Stoklund Olesen wrote: > > On Jul 21, 2010, at 7:44 AM, Ken Dyck wrote: > > Speaking of the rewriter, I've had some > problems recently where the > > rewriter replaces the last of the three > load instructions with a COPY > > instruction because isLoadFromStackSlot() > returns the same frame index > > for all

Hello LLVM, The ARM target sometimes adds an instruction with a virtual register in eliminateFrameIndex(): https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp This looks late for a virtual register to appear. Where is this vreg made real? Thanks, -steve

On Sat, 7 Oct 2006, [UTF-8] Rafael Esp?ndola wrote: >> This sounds like the ADJCALLSTACK DOWN/UP 'instructions' around the call >> aren't set right, or you have declared a SP offset. It doesn't look like >> the ARM backend does this, so this is probably the problem. > The ARM backend currently doesn't use a frame pointer. It uses the > same technique