similar to: [LLVMdev] Tablegen problem in LLVM 1.8

On Aug 9, 2006, at 06:17, Bram Adams wrote: > Today I downloaded LLVM 1.8 (until yesterday I used 1.7) and I > tried to build it (Slackware 10.2 with default GCC 3.3.6). However, > the build process fails each time it reaches lib/Target/XXX/ > XXXISelDAGToDAG.cpp for all backends (XXX=X86, ARM, ...) > > The NOINLINE-macro after each method's argument list and right

Ok, this is really complicated. I need some TableGen experts to help here. I need a little help doing a final bit of tblgen hacking. I've hacked tblgen to handle patterns like this: let AddedComplexity = 40 in { def : Pat<(vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:$src1))), (v2f64 (scalar_to_vector (loadf64 addr:$src2))),

I am working the AVR backend. It is still in the early stage. I got the following error:[ 86%] Building CXX object lib/Target/AVR/CMakeFiles/LLVMAVRCodeGen.dir/AVRISelDAGToDAG.cpp.obj AVRISelDAGToDAG.cpp C:\llvm-build\lib\Target\AVR\AVRGenDAGISel.inc(596) : error C2664: 'llvm::SDNode *llvm::SelectionDAG::SelectNodeTo(llvm::SDNode *,unsigned int,llvm::MVT,llvm::MVT,llvm::MVT,const llvm::SDValue

Hi, Gordon Henriksen wrote: > Is this patch incorporated on the 1.8 branch? > > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20060731/036455.html This patch does work (tried it out), but for some reason I get one more unexpected lib/test-failure in favor of an expected pass (see attachment). Kind regards, Bram Adams GH-SEL, INTEC, Ghent University (Belgium)

Hi, I'd like to understand the order in which patterns are searched during ISEL. In the example below, indices are searched in ascending order from 808 to 3305, then it goes back to 3259 and eventually it matches the wrong instruction. Why did go back from 3305 to 3259? In my XXXGenDAGISel.inc, I can see that the correct instruction is at index 3420 but it never got there. ISEL: Starting

Hi, after perusing through llc -debug output and stepping through the ARMGenDAGIsel.inc in the debugger, I would greatly like some help in tracking down a failing match to a pattern I specified: First, here is a snippet of a successful match (done in ARM mode) ISEL: Starting pattern match on root node: 0x1e7adf0: i32,ch = load 0x1e4c030, 0x1e78210, 0x1e78310<LD4[ConstantPool]> [ID=10]

On Wed, Jun 11, 2008 at 11:49 AM, Gordon Henriksen <gordonhenriksen at mac.com> wrote: > Could you please update to r52213 or later in svn and check whether > this error is resolved with your gcc? Latest trunk fixes that error. Next problem :) llvm[3]: Building ARM.td register information header with tblgen llvm[3]: Building ARM.td register names with tblgen llvm[3]: Building ARM.td

On Jun 25, 2009, at 4:38 PM, David Goodwin wrote: > Using the Thumb-2 target we see that ORN ( a | ^b) and BIC (a & ^b) > have similar patterns, as we would expect: > > defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node: > $RHS))>>; > defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node: >

On Thu, Jun 12, 2008 at 7:02 PM, Edd Barrett <vext01 at gmail.com> wrote: > gcc4.2 works fine. But it only works fine for svn snapshots. Your most recent release does not build on OpenBSD with gcc-4.2. llvm[3]: Building ARM.td instruction selector implementation with tblgen assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node

On Jun 25, 2009, at 6:06 PM, Evan Cheng wrote: > > On Jun 25, 2009, at 4:38 PM, David Goodwin wrote: > >> Using the Thumb-2 target we see that ORN ( a | ^b) and BIC (a & ^b) >> have similar patterns, as we would expect: >> >> defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not >> node:$RHS))>>; >> defm t2ORN :

It would be useful if you can post some example code and what you think the assembly code should look like. On Mar 26, 2009, at 5:41 PM, Robert Schuster wrote: > Hi, > I have reworked my previous example and got something which is > accepted > by tblgen: > > let isCall = 1, > Defs = [R0, R1, R2, R3, R12, LR, > D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { >

Hi, Now that clang is warning about unused functions, the self-host build is really noisy. The majority of the unused functions are generated by TableGen: /Volumes/Data/b/lib/Target/ARM/ARMGenDAGISel.inc:643:13: warning: unused function 'Predicate_t2_so_imm2part' [-Wunused-function] inline bool Predicate_t2_so_imm2part(SDNode *inN) const { ^ Specifically this FIXME in

I've run into a situation in isel where it seems like the selector is generating a cycle in the DAG. I have something like this: 0x215f140: v2f64 = llvm.x86.sse2.min.sd 0x215efd0, 0x21606d0, 0x215eb80 [0] 0x215efd0: i64 = Constant <647> [0] 0x21606d0: v2f64 = scalar_to_vector 0x213b8f0 [0] 0x213b8f0: f64,ch = load 0x213b780, 0x213aa90, 0x213b610 <0x2113690:0> alignment=8

On Mon, Jun 16, 2008 at 05:00:24PM +0100, Edd Barrett wrote: > On Thu, Jun 12, 2008 at 7:02 PM, Edd Barrett <vext01 at gmail.com> wrote: > > gcc4.2 works fine. > > But it only works fine for svn snapshots. Your most recent release > does not build on OpenBSD with gcc-4.2. > > llvm[3]: Building ARM.td instruction selector implementation with tblgen > assertion

In an attempt to add vector registers to my target, I ran into a problem. LLVM started to complain about not being able to infer types from the provided DAG patterns for several classes of instructions. After a discussion on the llvm-dev mailing list and IRC channel the recommendation was to make DAG patterns for these classes of instructions more specific. Which is what was done. However after

On 10/30/2012 04:52 PM, Tim Northover wrote: > Hi Heikki, > >> just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))] >> >> gives me error that extloav2i8 is not defined. > > I don't have a target to test this on, but looking at > include/llvm/Target/TargetSelectionDAG.td, there is an "sextloadvi8" > PatFrag, at least. I'd suggest

Hi Nikos > and when i try to call llc produces this error > > LLVM ERROR: Cannot select: 0x234bab0: f16 = fadd 0x234b8b0, 0x234c2b0 > [ORD=9] [ID=29] This error suggests things are working on the generic LLVM side (as I'd expect). It's what I'd expect to see for your code snippet if there wasn't a target-specific pattern that could handle the addition properly and

Hi David, > [(set GR32:$rD, globaladdr:$addr)] > It seems to have somehow managed to create a cycle in the DAG, which is > of course wrong. But how? When I write a similar pattern into the ARM .td files and look at (from the build directory) lib/Target/ARM/ARMGenDAGISel.inc, I see: /*56478*/ /*SwitchOpcode*/ 13, TARGET_VAL(ISD::GlobalAddress),// ->56494 /*56481*/

Add several .gitignore rules to various directories to ensure a clean worktree after a default build. Signed-off-by: Ramkumar Ramachandra <artagnon at gmail.com> --- Just cloned and built LLVM. This annoyed me. Here's a trivial patch. .gitignore | 10 ++++++++++ bindings/ocaml/llvm/.gitignore | 1 + docs/.gitignore

On Fri, Feb 19, 2016 at 6:10 AM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 2/18/2016 6:01 PM, Rail Shafigulin via llvm-dev wrote: > >> [(set SR:$rD, (Esenciasetflag (i32 GPR:$rA), (i32 >> immSExt16:$imm), (i32 Cond)))]> { >> > > I suspect that the "set SR:$rD" is the problem here. The Esenciasetflag