similar to: [LLVMdev] SSA virtuals -> Original variables

Dear LLVM'ers, I'm producing code for the PowerPC, and many often times it happens that the bytecodes generated by LLVM have phi-functions like: A4 = phi(A1, A2) A5 = phi(A1, A3) Where the 'A1' parameter appears in two different phi-functions. Could someone give me an example in "pseudo-assembly" that would produce code like that after being transformed into

Dear LLVM'ers, I am browsing the instruction schedulers available in llc, and there are many: -pre-RA-sched = {default, none, simple, simple-noitin, list-burr, list-tdrr, list-td} I looked into the sources in lib/CodeGen/SelectionDAG, and I could find implementation of Sethi-Ullman numbering, list scheduling, etc. Now, I wish I could find some comparison between the

Dear guys, I want to coalesce some copies, and I would like to know if there is any method that I can call, like JoinCopy from the old (LLVM 1.9) LiveIntervals class. I found it in SimpleRegisterCoalescing (LLVM 2.1), but I do not want to call this analysis, as I have my own. basically, I can determine that two virtuals do not overlap, and I know that it is safe to join them. In

On Thu, 12 Apr 2007, Fernando Magno Quintao Pereira wrote: >> I'm definitely interested in improving coalescing and it sounds like >> this would fall under that work. Do you have references to papers >> that talk about the various algorithms? > > Some suggestions: > > @InProceedings{Budimlic02, > AUTHOR = {Zoran Budimlic and Keith D. Cooper and Timothy

On Dec 15, 2007, at 4:45 PM, Fernando Magno Quintao Pereira wrote: > > Dear guys, > > I want to coalesce some copies, and I would like to know if > there is > any method that I can call, like JoinCopy from the old (LLVM 1.9) > LiveIntervals class. I found it in SimpleRegisterCoalescing (LLVM > 2.1), > but I do not want to call this analysis, as I have my own.

Dear Dave, Evan, thank you for answering. What I did was to remove the implementation of most of the methods of SimpleRegisterCoalescing and put them in a single class (RegisterCoalescer_Impl) that is not an analysis. Any class that wants these methods, can extend this class privately, or can use a reference to an RegisterCoalescer_Impl object. I wish it would be possible to go even

LiveVariables gives you something like liveness analysis: where each variable is alive, that is, across each basic blocks, where it is defined, and where it is killed. LiveIntervals gives you a linear representation of the variables as a set of intervals. Yes, it handle holes in the live ranges. There is a very nice description of these analysis and related data structures here:

Fernando Magno Quintao Pereira wrote: > LiveVariables gives you something like liveness analysis: where each > variable is alive, that is, across each basic blocks, where it is defined, > and where it is killed. If I read this correctly, it means that at each instruction there's a list of live variables? I'm trying to figure out how to get at this information to build the

On 11/23/07, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > Hi, Sanjiv, > > those passes operate on the whole machine function. Each machine > function contains many basic blocks. If a program has many functions, the > register allocator will be called as many times, i.e it does not do > interprocedural allocation. > > best, > >

Dear LLVM'ers (or whatever name you will soon have), I want to create a pass option, that I could pass at command line, and that would be visible among many different MachineFunction passes. It would be something like the join-liveintervals used in LiveIntervalAnalysis, but I want my option to be visible among many passes, and not only one. I browsed the documentation, but I did not

Hi, again, I think you can do it in the same way that the other allocators have been coded, i.e extend RA, register the pass and so forth. I am not sure about the best way to pass information among a run of RegAlloc to the other, maybe the other guys in the list could suggest something. Yet, you can always dump it into a file, and read it again, everytime it is necessary. Remember that

Thank you Chris. I will try to implement the TwoAddress pass to run on machine code. Why it has not been originally implemented to run on machine code? Is there anything that makes it troublesome after RA has been performed? Could you tell me if the transformations below are correct? 1) a := b op c --> a := b --> a := b a := a op c a

Thanks again. One more question here: Since the regalloc works once per function, do I stil have access to the Call graph? Just saving information between regalloc passes for different functions may not be enough for my case. I will need to maintain the regalloc info of various passes in the call graph order. Anyways thanks for your inputs. I will get back if I need to learn more. Sanjiv On Nov

Hi, guys, What is the opcode of the instruction to swap two registers in X86? After updating my LLVM branch, I realized that there is no longer an opcode for xchg with two register operands in X86GenInstrNames.inc. I found only instructions to swap memory and registers: XCHG16rm, XCHG32rm, XCHG64rm and XCHG8rm. I am updating from LLVM 2.1 to current trunk. The names that I was

Fernando Magno Quintao Pereira wrote: >> I'm not sure about one thing: you assign stack slot to each new register you >> replace the spilled one with. And then you need to allocate physical >> registers to them. Is it possible to assign physical register to the virtual >> one which has a stack slot already? >> > > Yes. The stack slot is the place where the

Guys, I think I figure out the way that the current LLVM allocators are handling IMPLICIT_DEF's. One question more: why are you adding null length intervals to IMPLICIT_DEF instructions? If they were non-null, I think the code to handle them would be more homogeneous, e.g a traversal of the intervals during register allocation would already reveal virtuals defined implicitly. best,

Dear guys, I am in need of more of your help. I'm implementing a register allocator, and I am having problems to make it produce correct code. Consider this program here: int main(int argc, char ** argv) { int i, j, sum; i = argv[0][0]; j = argv[0][1]; sum = (i + j) * j; printf("Sum = %d\n", sum); } that maps to this llvm bytecode: entry (0xa785590, LLVM

Hi, Nicolas, I have been talking to Andre about this project. Let me add my two cents: > I don't get it. What is the cons then of a simulation? The tradeoff, IMHO, is as follows: simulation: it does not add instructions to LLVM IR. Instead, it builds an interval representation for each variable. Each interval represents a variable in SSI form, and will be associated to one or

I'm just starting to dive into llvm, hoping to implement a good graph coloring register allocator. I gather that this has been discussed before. What is the RegAllocGraphColoring.cpp currently in the sources? It seems to be the Fred Chow algorithm but it's not mentioned in the documentation anywhere. Does it work? -Dave

I was using them to do SSA-elimination after register allocation. I can implement swaps using three XOR's, but then the code becomes a little bigger and slower. I think even for the sake of completeness, the X86 back-end should offer the possibility of swapping two registers with one single instruction. Do you guys think there is any possibility that those instructions could come back to