similar to: [LLVMdev] Changing number of registers

Hi LLVMers, what is the status of breaking critical edges in machine functions? I just compiled the top of the LLVM tree, and I found llvm/CodeGen/BreakCriticalMachineEdge.h. But this file seems not to be up-to-date with the other classes in the top of the tree. For instance, it calls isTerminatorInstr on llvm::TargetInstrInfo, but this method is no longer there. If I want to break

Dear LLVMers, we have released a tool that uses LLVM to insert OpenACC or OpenMP 4.0 directives in programs. You can use the tool online here: http://cuda.dcc.ufmg.br/dawn/. Our tool, dawn-cc, analyzes the LLVM IR to infer the sizes of memory chunks, and to find dependences within loops. After that, we use debug information to translate the low-level information back into annotations that we

Dear LLVMers, I need help with one error in my register allocator. I am getting errors when folding instructions for the x86 (it does not happen when I use the PowerPC as target). The problem is that, when I execute something like: mi = mbb->insert(mbb->erase(mi), fmi), where mbb is a MachineBasicBlock, valgrind gives this error message: Address 0x42C62B0 is 24 bytes inside a block

Hi Florian, we though about using UIUC, like in LLVM. Do you guys know if that could be a problem, given that we are mining the functions from github? > Have you thought about integrating the benchmarks as external tests into LLVM’s test-suite? That would make it very easy to play around with. We did not think about it actually. But we would be happy to do it, if the community accepts

Fernando, The code there should be more or less functional, though it's not currently used by anything. Eventually it should probably be moved to a method on MachineBasicBlock. The API breakage you're seeing is because some methods moved around. Feel free to fix it. :-) --Owen On Jan 26, 2008, at 6:31 PM, Fernando Magno Quintao Pereira wrote: > > Hi LLVMers, > >

Hi, > On Dec 31, 2016, at 8:33 AM, Fernando Magno Quintao Pereira via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Dear LLVMers, > > we have released a tool that uses LLVM to insert OpenACC or OpenMP > 4.0 directives in programs. You can use the tool online here: > http://cuda.dcc.ufmg.br/dawn/. Our tool, dawn-cc, analyzes the LLVM IR > to infer the sizes of

LLVMers, The oversight group has been kicking around the idea of getting a better version control system than CVS. The problem is, we're not quite sure what "better" means. So, we thought we'd ask your opinions. If you're interested in this topic (and you should be if you're actively developing), please have a look at this site:

Dear LLVMers, we, at UFMG, have been building a large collection of compilable benchmarks. Today, we have one million C files, mined from open-source repositories, that compile into LLVM bytecodes (and from there to object files). To ensure compilation, we perform type inference on the C programs. Type inference lets us replace missing dependencies. The benchmarks are available at:

Hello, llvmers. Could someone explain me a little about the opt tool? I am having problems to load a MachineFunctionPass using opt. I have this pass: #include "llvm/Pass.h" #include "llvm/Function.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include <iostream> using namespace llvm; namespace { struct MacFoo : public MachineFunctionPass { virtual

Dear LLVMers, Does anyone know what the latest is w.r.t a FORTRAN front-end for LLVM? Is anyone expecting to have typical f90/f95 programs compiling to LLVM this year, or next? (I'm aware of the "NAG hack" and various other f2c-type approaches, but they give me a strange feeling in my tummy.) Duraid

On Mon, 1 May 2006, Fernando Magno Quintao Pereira wrote: > Hello, llvmers. Could someone explain me a little about the opt tool? I am > having problems to load a MachineFunctionPass using opt. I have this pass: MachineFunctionPass's cannot be used as part of opt, they can only be used as part of LLC. Further, you have to explicitly modify the target you are interested in to add it

Hi, LLVMers, has someone implemented bitwidth analysis for LLVM? I was looking for something similar to the bitwise compiler described in "Bidwidth analysis with application to silicon compilation, by Mark Stephenson, Jonathan Babb and Saman Amarasinghe" e.g.: http://portal.acm.org/citation.cfm?id=349299.349317 all the best, Fernando

> > Thank you Chris. I will try to implement the TwoAddress pass to run on > > machine code. Why it has not been originally implemented to run on > > machine code? > > I'm not sure what you mean. It definitely does run on machine code. I was thinking that it only transformed instructions with virtual registers because of this code in the TwoAddressInstructionPass.cpp:

On Mon, 26 Jun 2006, Fernando Magno Quintao Pereira wrote: >>> Thank you Chris. I will try to implement the TwoAddress pass to run on >>> machine code. Why it has not been originally implemented to run on >>> machine code? >> >> I'm not sure what you mean. It definitely does run on machine code. > > I was thinking that it only transformed

Hi everyone, Reid said: > Of the tools available, it seems that only subversion, arch, and > monotone are suitable for our purposes. But, we'd love to hear your > thoughts; especially if you have first-hand experience with these tools. Apart from using CVS as a client (as everyone does), I've only ever used Aegis (previous employer, for ~3 years) and Perforce (the employer

Hi, everyone. I' have three set of registers - read-only regs, general purpose regs (read and write), and write-only regs. How should I partition them into different RegisterClasses so that I can easy define the instruction? All RegisterClasses must be mutally exclusive. That is, a register can only be in a RegisterClass. Otherwise TableGen will raise an error message. def

On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote: > 2005/7/23, Chris Lattner <sabre at nondot.org>: >> What does a 'read only' register mean? Is it a constant (e.g. returns >> 1.0)? Otherwise, how can it be a useful value? > > Yes, it's a constant register. > > Because the instruction cannot contain an immediate value, a constant > value may be stored in

2005/7/23, Chris Lattner <sabre at nondot.org>: > > What does a 'read only' register mean? Is it a constant (e.g. returns > 1.0)? Otherwise, how can it be a useful value? Yes, it's a constant register. Because the instruction cannot contain an immediate value, a constant value may be stored in a constant register, and it's defined _before_ the program starts by

On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote: > I' have three set of registers - read-only regs, general purpose regs > (read and write), and write-only regs. How should I partition them > into different RegisterClasses so that I can easy define the > instruction? [snip] > def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest, >

All registers in my hardware are 4-element vector registers (128-bit). Some are floating point registers, and the others are integer registers. I typedef two packed classes: [4 x float] and [4 x int], and add an enum 'packed' to MVT::ValueType (ValuesTypes.h). I declared all 'RegisterClass'es to be 'packed' (first argument of RegisterClass): def GeneralPurposeRC :