similar to: [LLVMdev] Live ranges of physical registers

<div class="socmaildefaultfont" dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div class="socmaildefaultfont" dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" > </div> <div dir="ltr" >Hi all,</div> <div dir="ltr" > </div> <div

<div class="socmaildefaultfont" dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" style="font-family:Arial;font-size:10.5pt" ><div dir="ltr" >Matthias,</div> <div dir="ltr" > </div> <div dir="ltr" >Thanks for the response.</div> <div

Dear guys, After compiling 188.ammp, one of spec floating point benchmarks, using the linear scan register allocator, I got 34 spills, but only 28 store instructions. These data were given by -stats. Is this number correct? I mean, the number of stores should be equal or greater than the number of spills, shouldn't it? Best regards, Fernando

On Thu, 6 Nov 2003, Michelle Strout wrote: > I think some clarifications and examples would be helpful. No problem. :) > - LLVM is in SSA. It is in SSA before alias analysis has been > >>>> performed. With OA, it has been mentioned that the SSA generation > >>>> is > >>>> incorrect because it doesn't take alias analysis information into

Chris and everyone else, Below I summarize my understanding of what llvm does when converting to SSA and a clarification on why backward dataflow analyses can not be performed on "just" SSA. >> Scalar variables still have a stack location associated with them, >> don't they? > > No, they don't. All scalar values in LLVM represent "virtual >

On Monday 31 March 2008 00:57, Chris Lattner wrote: > On Mar 30, 2008, at 10:42 PM, David A. Greene wrote: > >> SSA form, it is reasonable to say "give me the first def" and expect > >> it to be the only def. For multiply defined values like physregs, > >> this is not true, because the reg can have multiple defs. > > > > Gotcha. This is exactly

I am observing poor instruction scheduling in my out-of-tree target. The problem is an over-constrained scheduling DAG. In particular, the DAG includes spurious output dependencies on physical, non-register-allocatable registers. MISched already includes code to avoid this problem. However that code relies on information clobbered by the earlier pass LiveVariables. I wonder whether this is a

Hi, thank you for your explanations. In order to get a pre-RA scheduling, I would need something like: - LiveVars - PhiElim - TwoAddr - LiveIntervals - Coalescing - Scheduler (new) - SlotIndexing - LiveIntervals2 (new) - RegAllocMy qeustion then is, is it really so difficult to create the live intervals information, with modifications to the original algorithm, or even from scratch?

I am looking at results from analyzePhysReg, and am getting results a little different than I expected for x86. The call to this is coming from this code in llvm::MachineBasicBlock::computeRegisterLiveness 1163 MachineOperandIteratorBase::PhysRegInfo Analysis = 1164 ConstMIOperands(I).analyzePhysReg(Reg, TRI); The instruction I being analyzed is: %BX<def> = MOV16rm

I'm forwarding this to llvmdev so it doesn't get lost in the sea of commits... -Dave ---------- Forwarded Message ---------- Subject: Re: [llvm-commits] [llvm] r48521 - in /llvm/trunk: include/llvm/CodeGen/LiveVariables.h lib/CodeGen/LiveVariables.cpp test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll test/CodeGen/X86/x86-64-ret0.ll

>-----Original Message----- >From: Quentin Colombet [mailto:qcolombet at apple.com] >Sent: Thursday, December 03, 2015 4:43 PM >To: Smith, Kevin B <kevin.b.smith at intel.com> >Cc: llvm-dev at lists.llvm.org >Subject: Re: [llvm-dev] analyzePhysReg question > > >> On Dec 3, 2015, at 4:35 PM, Smith, Kevin B via llvm-dev <llvm- >dev at lists.llvm.org>

Hello all Currently I want to use the accurate liveness information when writing a *target independent* FunctionPass based on LLVM. The one I can find is LiveValues, a FunctionPass. But it doesn't use classic dataflow equation and can only provide approximate and conservative result. The another one is LiveVariables which use classic data flow equation, but it comes from Clang's analysis

> On Dec 3, 2015, at 5:36 PM, Quentin Colombet via llvm-dev <llvm-dev at lists.llvm.org> wrote: > >> >> On Dec 3, 2015, at 5:11 PM, Smith, Kevin B <kevin.b.smith at intel.com <mailto:kevin.b.smith at intel.com>> wrote: >> >> >> >>> -----Original Message----- >>> From: Quentin Colombet [mailto:qcolombet at apple.com

On Thu, 7 Jun 2012 22:14:00 -0700 Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > > > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > > Predecessors according to CFG: BB#0 BB#1 > > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, > >

Evan, >A physical register cannot be live across the block. So it >must have a use in the block or it must be marked dead. From >your dump, it looks like the CCFLAGS defs are not being marked >dead. It's unclear where things went wrong, but you can step >through LiveVariables to debug this. Thanks for your response. I did quite some stepping through the llc passes, and it

So if I create a value with a DAG.getUndef(myVT); call during instruction legalization, how can I access that value as input in another BB/DAG (also during instruction legalization) without worrying about live-ins and/or phi nodes? Can I create a single virtual register and build both a CopyToReg and a CopyFromReg node with it? I assumed that would break SSA. Perhaps I should have said that what

On Thu, May 26, 2011 at 15:07:24 +0200, Jonas Paulsson wrote: > In order to get a pre-RA scheduling, I would need something like: > - LiveVars > - PhiElim > - TwoAddr > - LiveIntervals > - Coalescing > - Scheduler (new) > - SlotIndexing > - LiveIntervals2 (new) > - RegAlloc > My qeustion then is, is it really so difficult to create the live intervals

Hi (Jakob), in reference to the prior message below, I have the following follow-up questions, as I also need a scheduling pass prior to regalloc. I need to do this in order to set VLIW-flags, so that the RA is aware of several MI's per cycle with a redefined LiveRange::overlap-function. On a multiple-issue cycle, a register that gets killed can be reused by another MI - these live ranges do

On Jun 7, 2012, at 10:54 PM, Hal Finkel wrote: > For example, sometimes LiveIntervals asserts with: > register: > %CTR8 > clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446: > void llvm::LiveInterval > s::handlePhysicalRegisterDef(llvm::MachineBasicBlock*, > llvm::MachineBasicBlock::iterator, llvm::SlotIndex, > llvm::MachineOperand&,

On Thu, 6 Nov 2003, Michelle Strout wrote: > Those of us working on the OpenAnalysis project have been looking at > LLVM recently (excellent job on the website BTW). Thanks! I'm just one of the many people who have worked on it though, the praise belongs to them as much as it does to me. :) > This includes researchers at Rice, Argonne, and LLNL. Great! > John Mellor-Crummey