similar to: [LLVMdev] floating point exception and SSE2 instructions

Hi Simon, The x86 backend does generate scalar SSE2 instructions. For your example, it should emit something like: .text .align 4 .globl _sum_d _sum_d: subl $12, %esp movl 20(%esp), %eax movl 16(%esp), %ecx cmpl $0, %eax jne LBB_sum_d_2 # cond_true.preheader LBB_sum_d_1: # entry.bb9_crit_edge pxor %xmm0,

On Thu, 9 Nov 2006, Ryan M. Lefever wrote: Sorry I never responded to this: > In the literature (see below for a reference), when a dominance frontier > is computed, it is computed from a CFG that contains a dummy entry node > and dummy exit node. Further, those dummy nodes are potential members > of the (post-)dominance frontier for a given basic block. In LLVM, I > could not

Dear all, after optimizing a small LLVM example program (i.e., with opt -O3), the resulting code contains several basic blocks, which I consider identical or redundant. For instance, return: ; preds = %min.exit ret i32 0 bb15: ; preds = %min.exit ret i32 0 or, bb7.i:

In the literature (see below for a reference), when a dominance frontier is computed, it is computed from a CFG that contains a dummy entry node and dummy exit node. Further, those dummy nodes are potential members of the (post-)dominance frontier for a given basic block. In LLVM, I could not figure out a way to determine if the dummy entry node is a member of the post-dominance frontier of

Would it make sense to have a similar pass that operates on llvm main IR? On Sat, May 8, 2010 at 5:15 PM, Dale Johannesen <dalej at apple.com> wrote: > The branch folding pass does this, but it operates later, on the > target-dependent form in llc. > > On May 8, 2010, at 8:48 AM, Heinz Riener wrote: > >> Dear all, >> >> after optimizing a small LLVM example

I got some R code that I don't understand. Question as comment in code //where is t comming from, what is phi inverse rAC <- function(name, n, d, theta){ #generic function for Archimedean copula simulation illegalpar <- switch(name, clayton = (theta < 0), gumbel = (theta < 1), frank = (theta < 0), BB9 = ((theta[1] < 1) | (theta[2] < 0)), GIG = ((theta[2] < 0) |

The branch folding pass does this, but it operates later, on the target-dependent form in llc. On May 8, 2010, at 8:48 AM, Heinz Riener wrote: > Dear all, > > after optimizing a small LLVM example program (i.e., with opt -O3), > the > resulting code contains several basic blocks, which I consider > identical > or redundant. For instance, > > return:

Hi all, I've run into problems compiling the llvm-gcc frontend on x86_64. Is this not supported, or am I making an error somewhere? The procedure I followed was: 1. Download LLVM 2.0 source as a tarball (from a few days ago, during the testing phase). 2. Download the llvm-gcc4 source today, as a tarball. 3. Extract both. 4. Configure LLVM as: ../src/configure --prefix=`pwd`../install

Hi Warren, You have the -m32 flag set, but it's still giving you this: > Warning: Generation of 64-bit code for a 32-bit processor requested. > Warning: 64-bit processors all have at least SSE2. But are you sure you want to compile the LLVM-GCC source? You should use the binaries unless absolutely necessary. -bw On May 24, 2007, at 10:34 PM, Warren Armstrong wrote: > Hi all,

Eugene Toder wrote: > Would it make sense to have a similar pass that operates on llvm main IR? > The unify exit return node (-mergereturn?) pass should take care of the first example. The -simplifycfg option might take care of the second example. Both work on LLVM IR. -- John T. > On Sat, May 8, 2010 at 5:15 PM, Dale Johannesen <dalej at apple.com> wrote: > >>

On Jul 23, 2008, at 8:47 PM, kapil anand wrote: > > Specifically, I need a way to represent indirect branch instruction > (in binary) as an equivalent LLVM instruction. With switch > instruction , I would have to list all the possible targets and then > initialize the corresponding instruction. I was just thinking > whether it might be possible to have some kind of

Hi, Can any llvm pass change simple return branch into select/return pair? For example: define i10 @mod_N(i10 zeroext %a) zeroext { entry: %tmp2 = icmp ugt i10 %a, -400 ; <i1> [#uses=1] br i1 %tmp2, label %cond_true, label %return cond_true: ; preds = %entry %tmp5 = add i10 %a, 400 ; <i10> [#uses=1] ret i10 %tmp5 return: ; preds = %entry ret

According to the docs, InsertBranch should only be called if AnalyzeBranch returns success. But in targets (like ARM or Sparc) that don't implement them, the following test fails: ----------------------------------- void %__gcov_init() { entry: switch uint 0, label %cond_true.i [ uint 0, label %UnifiedReturnBlock uint 875573313, label

Specifically, I need a way to represent indirect branch instruction (in binary) as an equivalent LLVM instruction. With switch instruction , I would have to list all the possible targets and then initialize the corresponding instruction. I was just thinking whether it might be possible to have some kind of indirect branch where label is a "variable" and not an explicit label present in

I am working on a transform that uses an scc_iterator on a program's CallGraph. However, I am running into a problem in which not all callees are being processed before callers, leading me to believe there might be a bug. In particular, this is happening in a case where a callee is a function pointer. I ran bugpoint and have included the bugpoint-reduced-simplified.ll below. If

On Sun, Feb 5, 2017 at 12:25 PM, Nuno Lopes <nunoplopes at sapo.pt> wrote: > Hi Daniel, > > Many thanks for working on this! > SSI/e-SSA is the only way I'm aware of for doing efficient sparse > analyses, so I'm definitely in favor of adding support for it in LLVM! > > I read the discussion so far and did a cursory review of the patches, and > I have just a

Dear there, Is the following phi instruction valid? %j_8 = phi i32 [ %j_100, %"<bb 13>" ], [ %j_9133, %"<bb 10>" ], [ %j_9133, %"<bb 9>" ] Variable %j_9133 is in bb 9. And also this one: %D.1898_8.i = phi i32 [ %D.1898_27.i, %"<bb 18>.i" ], [ -1, %"<bb 23>" ], [ %D.1776_193, %"<bb 4>], [ %D.1776_193,

Hi Warren, you can try to configure with the following export CFLAGS="-m64" export LDFLAGS="-L/usr/lib64" LLVM: ../src/configure --prefix=`pwd`../install --enable-optimized --enable-jit --enable-targets=host-only make LLVM-GCC: ../llvm-gcc4-2.0.source/configure --prefix=`pwd`../install --program-prefix=llvm- --enable-llvm=/home/warren/llvm/obj/ --enable-languages=c,c++

On Oct 20, 2010, at 7:46 AM, Roland Scheidegger wrote: > On 20.10.2010 05:00, Jakob Stoklund Olesen wrote: >> Look in X86InstrControl.td. The call instructions are all prefixed >> by: >> >> let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, FP0, FP1, FP2, >> FP3, FP4, FP5, FP6, ST0, ST1, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, >> XMM0, XMM1, XMM2, XMM3,

Is llvmc meant for compilation? $ llvmc -c a.c -o a.o /usr/src/llvm/dist/etc/llvm/c:55: Error: Expecting output type value /usr/src/llvm/dist/etc/llvm/c had 1 errors. Terminating. The offending line contains: optimizer.output = bytecode which doesn't seem to be understood by llvmc. If I uncomment this line, I get another error message: $ llvmc -c a.c -o a.o llvmc: Can't find program