similar to: [LLVMdev] The live interval of write-only registers

On Tue, 13 Dec 2005, Tzu-Chien Chiu wrote: > In my ISA, some registers are write-only. These registers serve as > output ports, writing to these registers will output the values to an > external device. They cannot be read. So their live intervals should > not be joined with any other registers. Ok. Since they are not really registers in the sense that LLVM is used to, I

2005/12/13, Chris Lattner <sabre at nondot.org>: > > For example, this a code snippet for the file generated by the TableGen tool: > ... > > Somewhere in my code, I have to write: > > unsigned opcode = MI->getOpcode(); // MachineInstr* > > if (CMPfaaaa == opcode || > > CMPfaaar == opcode || > > CMPfaara == opcode || > > ...

2005/12/13, Chris Lattner <sabre at nondot.org>: > On Tue, 13 Dec 2005, Tzu-Chien Chiu wrote: > > > In my ISA, some registers are write-only. These registers serve as > > output ports, writing to these registers will output the values to an > > external device. They cannot be read. So their live intervals should > > not be joined with any other registers. >

I don't understand the following code snippet in LiveIntervalAnalysis.cpp. Why changing the type of the opreand from a virtual register to a machine register? The register number (reg) is still a virtual register index (>1024). bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { // perform a final pass over the instructions and compute spill // weights, coalesce

You need to specify sub-register == super-register, idx relationship. See X86RegisterInfo.td: def x86_subreg_8bit : PatLeaf<(i32 1)>; def x86_subreg_16bit : PatLeaf<(i32 2)>; def x86_subreg_32bit : PatLeaf<(i32 3)>; def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], [AL, CL,

On Thu, 2008-10-02 at 11:19 -0700, Evan Cheng wrote: > > On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote: > > > What’s the value produced by an INSERT_SUBREG node? Is it a chain? > > > No, insert_subreg returns a value: > > > v1 = insert_subreg v2, v3, idx > > > v1 and v2 will have the same type, e.g. i16, and v3 must have a >

On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: > You need to specify sub-register == super-register, idx relationship. > See X86RegisterInfo.td: > > def x86_subreg_8bit : PatLeaf<(i32 1)>; > def x86_subreg_16bit : PatLeaf<(i32 2)>; > def x86_subreg_32bit : PatLeaf<(i32 3)>; > > def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, >

Didn't SparcV9 backend implement list scheduling? 2005/12/16, Chris Lattner <sabre at nondot.org>: > On Thu, 15 Dec 2005, thean kiat sew wrote: > > I am planning to use list scheduling on LLVM instructions. > > Any recommendation on how to start ? As in which codes in LLVM that I need > > to look at. > > We don't currently have a list scheduler in the

A question about how the memory of object in LLVM are managed. I dived in some source files but still don't have any idea how the memory of MachineInstr object are managed. It doesn't look like reference counting. I'm writing an instruction scheudling code, the new order of MachineInstr* in a MachineBasicBlock is stored in a "schedule". All MachineInstr* in

Thanks, I think it can solve my problem. But please allow me to explain the hardware in detail. Hope there is more elegant way to solve it. The hardware is a "stream processor". That is, It processes samples one by one. Each sample is associated with several 128-bit four-element vector registers, namely: * input registers - the attributes of the sample, the values of the registers

The automated tests seems not run periodically. Some builds are even broken (http://llvm.cs.uiuc.edu/testresults/X86-niobe/), and some failed (http://llvm.cs.uiuc.edu/testresults/SparcV9/). Will there be another automated test be scheduled before the next release? On 11/10/05, Bill Wendling <isanbard at gmail.com> wrote: > Frequently releasing software can be a good thing. Especially

VLIW (Very Long Instruction Word) is a long instruction format (called "group" hereafter) contains several instructions. These instructions are not dependent on each other and could be issued in a single cycle. At this moment there is no correspondent class for VLIW. MachineInstr object can only represent one instruction. Usually the number of instructions in a group is fixed. The

On Oct 15, 2008, at 5:29 AM, sanjiv gupta wrote: > On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: >> You need to specify sub-register == super-register, idx relationship. >> See X86RegisterInfo.td: >> >> def x86_subreg_8bit : PatLeaf<(i32 1)>; >> def x86_subreg_16bit : PatLeaf<(i32 2)>; >> def x86_subreg_32bit : PatLeaf<(i32

LiveInterval.cpp. // that v is live at i'. In this implementation intervals can have holes, // i.e. an interval might look like [1,20), [50,65), [1000,1001). Each // individual range is represented as an instance of LiveRange, and the whole // interval is represented as an instance of LiveInterval. What cause these holes? -- Tzu-Chien Chiu - XGI Technology, Inc. URL:

Dear all: To write a compiler for Microsoft Direct3D shaders from our hardware, I have a program which translates the Direct3D shader assembly to LLVM assembly. I added several intrinsics for this purpose. It's a vector ISA and has some special instructions like: * rcp (reciprocal) * frc (the fractional portion of each input component) * dp4 (dot product) * exp (exponential) * max, min These

On Wed, 2008-10-15 at 10:08 -0700, Evan Cheng wrote: > On Oct 15, 2008, at 5:29 AM, sanjiv gupta wrote: > > > On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote: > >> You need to specify sub-register == super-register, idx relationship. > >> See X86RegisterInfo.td: > >> > >> def x86_subreg_8bit : PatLeaf<(i32 1)>; > >> def

I have a WLS regression with 1 dependent variable and 3 independent variables. I wish to constrain the predicted values (the fitted values) so that they are greater than zero (i.e. they are positive). I do not know how to impose this constraint in R. Please respond if you have any suggestions. There are some previous postings about constraining the coefficients, but this won't accomplish

The BGL (Boost Graph Library) defines tie(), which is exactly what the tie() defined in STLExtras.h. The header files of GBL use boost::tie(), and other boost libraries use boost::tie() too. How to resolve the ambiguity for compiler? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

On Thu, 15 Dec 2005, Tzu-Chien Chiu wrote: > To write a compiler for Microsoft Direct3D shaders from our hardware, > I have a program which translates the Direct3D shader assembly to LLVM > assembly. I added several intrinsics for this purpose. > It's a vector ISA and has some special instructions like: > * rcp (reciprocal) > * frc (the fractional portion of each input

Frequently releasing software can be a good thing. Especially when it gets to a point where you have a stable CVS version and many new features/bug fixes. -bw On 10/11/05, Chris Lattner <sabre at nondot.org> wrote: > > Hi All, > > It has been entirely too long since the last release, and we have plenty > of goodies for a very solid release. Do people find releases useful,