Displaying 20 results from an estimated 200 matches similar to: "[LLVMdev] Help on LLVM Instrumentation"
2004 May 21
1
[LLVMdev] Re: LLVMdev digest, Vol 1 #292 - 4 msgs
Hi,
Thank Brian Gaeke so much.
Following TraceBasicBlocks.cpp, I modified the code as below and could insert instruction or function I need into anywhere in Module.
But it works well without BB->getInstList().push_back(InstrCall), and if I add the BB->getInstList().push_back() following new CallInst(), I got error information when runing opt. What is the reason for it? And is it necessary
2010 Apr 08
4
[LLVMdev] How to Load a Value?
Hello,
I have a problem of generating a load instruction. The LLVM bytecode is:
------------------------
entry:
...
%2 = call i32 (...)* @atoi(i8*%1) nounwind
/*<- Insertpos*/
...
--
bb1:
..
%5 = icmp sgt i32 %2, %i.0
...
-----------------
Now I have
pb: pointer to the Value object of *%2* of bb1.
Here, I want to generate a load instruction and I did it as:
new LoadInst(pb,
2012 Aug 28
2
[LLVMdev] Assert in LiveInterval update
Andy,
I've described that issue (see below) when you were out of town... I think
I am getting more context on it. Please take a look...
So, in short, when the new MI scheduler performs move of an instruction, it
does something like this:
// Move the instruction to its new location in the instruction stream.
MachineInstr *MI = SU->getInstr();
if (IsTopNode) {
2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
Andy, Lang,
Thanks for the suggestion.
I have spent more time with it today, and I do see some strange things in
liveness update. I am not at the actual cause yet, but here is what I got so
far:
I have the following live ranges when I start scheduling a region:
R2 = [0B,48r:0)[352r,416r:5)...
R3 = [0B,48r:0)[368r,416r:5)...
R4 = [0B,32r:0)[384r,416r:4)...
R5 = [0B,32r:0)[400r,416r:4)...
2011 May 18
3
[LLVMdev] access array problem
Hi,
I want to access an array in my instrumentation code. For example:
GlobalVariable:
int *counter; //counter the number of load/store operations in run-time
int *counterArray; //record the load/store addresses
//increase the counter if a load/store is performed
std::vector<Constant *>index(2);
index[0] = Constant::getNullvalue(Type:getInt32Ty(Context));
index[1] =
2012 Aug 28
0
[LLVMdev] Assert in LiveInterval update
On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote:
>
> I've described that issue (see below) when you were out of town... I think
> I am getting more context on it. Please take a look...
>
> So, in short, when the new MI scheduler performs move of an instruction, it
> does something like this:
>
> // Move the instruction to its new
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
Hi Sergei, Andy,
Sorry - I got distracted with some other work. I'm looking into this and
PR13719 now. I'll let you know what I find out.
Sergei - thanks very much for the investigation. That should help me pin
this down.
Cheers,
Lang.
On Tue, Aug 28, 2012 at 2:33 PM, Sergei Larin <slarin at codeaurora.org> wrote:
> Andy, Lang,
>
> Thanks for the suggestion.
>
2011 Dec 05
0
[LLVMdev] RFC: Machine Instruction Bundle
On Dec 2, 2011, at 12:40 PM, Evan Cheng wrote:
> There have been quite a bit of discussions about adding machine instruction bundle to support VLIW targets. I have been pondering what the right representation should be and what kind of impact it might have on the LLVM code generator. I believe I have a fairly good plan now and would like to share with the LLVM community.
Let me add some
2010 Apr 08
0
[LLVMdev] How to Load a Value?
Zheng Wang <jason.wangz at gmail.com> writes:
> I have a problem of generating a load instruction. The LLVM bytecode is:
>
> ------------------------
> entry:
> ...
> %2 = call i32 (...)* @atoi(i8*%1) nounwind
> /*<- Insertpos*/
> ...
>
> --
> bb1:
> ..
> %5 = icmp sgt i32 %2, %i.0
> ...
> -----------------
>
>
> Now I have
>
2012 Aug 17
0
[LLVMdev] Assert in LiveInterval update
Andy, Jacob,
I have ported Hexagon MI scheduler to use the new scheduler
infrastructure, but one of my tests triggers an assert in LiveInterval
update. On the surface it does not make much sense to me, so I wonder if
this is something you readily recognize, before I try to prop it open...
The assert is:
lib/CodeGen/LiveInterval.cpp:266: llvm::LiveRange*
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
Hi Lang,
Just one more quick question. in LiveIntervalAnalysis.cpp In
SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx)
Did you really mean to use
for (MachineRegisterInfo::use_nodbg_iterator
UI = MRI.use_nodbg_begin(Reg),
UE = MRI.use_nodbg_end();
UI != UE; UI.skipInstruction()) {}
Aren't we currently dealing with units,
2011 May 18
0
[LLVMdev] access array problem
Hi Tan Guangming,
> I want to access an array in my instrumentation code. For example:
>
> GlobalVariable:
> int *counter; //counter the number of load/store operations in run-time
> int *counterArray; //record the load/store addresses
strictly speaking these are not arrays, they are pointers. Also, you have
written them in some kind of C-style idiom. What are the declarations
2005 Feb 07
2
[LLVMdev] Segmentation Fault(Modifying BasicBlockPlacement.cpp)
On Mon, 7 Feb 2005, Tanu Sharma wrote:
> I have been trying to randomize blocks in a program and modified
> "BasicBlockPlacement.cpp" for the purpose but getting segmentation
> fault.I am not able to determine the problem.Can anyone please decrypt
> these error messages or suggest what might be the possible cause of
> failure?
I'd be happy to fix this, but I need
2012 Aug 15
3
[LLVMdev] MI bundle liveness attributes
On Aug 13, 2012, at 8:34 AM, Sergei Larin <slarin at codeaurora.org> wrote:
> Andy,
>
> Yes, this is what Arnold has suggested also, and from this point it looks
> like it should work, but it will require parsing the bundle every time we
> care to know whether this is a real use or a conditional def. This might
> become awkward... but I guess I should provide a better
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
Hello Jakob and everyone,
I am observing an issue with MCRegUnitIterator in my back end, and trying
to reverse engineer some of the table gen magic around it, but if you or
someone readily knows the answer, I would highly appreciate it.
Here is the problem.
In my back end we have a rather simple int register file structure:
// Integer registers.
def R0 : Ri< 0, "r0">,
2005 Feb 07
0
[LLVMdev] Segmentation Fault(Modifying BasicBlockPlacement.cpp)
Thanks a lot for replying Chris,
I m trying to randomize the blocks in a program.I generate a random number( between the
current "InsertPos" and the last block), and then iterate through the list of basicblocks , picking up block with position equal to that of the random number and place it into the current InsertPos and increment InsertPos.
Running it like this:
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
Lang,
I think I am getting closer to understanding this. The findLastUseBefore()
should probably look something like this:
// Return the last use of reg between NewIdx and OldIdx.
SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
SlotIndex LastUse = NewIdx;
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
for (MCRegUnitRootIterator Roots(Reg,
2010 Nov 23
2
[LLVMdev] how to get a void type value in llvm
Hi, I want to insert a function with a void type parameter,
for example: int foo(void);
OI declared
fcall2 = M.getOrInsertFunction("foo",
IntegerType::get(M.getContext(), 32),
Type::getVoidTy(M.getContext()));
then the question is how to get the void type value to make the
CallInst inserted sucessfully? (what should be ********)
CallInst::Create(fcall2, ******,
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
Hi Sergei,
Register units != sub registers.
Register units are an abstraction to describe overlapping of registers
effectively.
You probably wanted to use MCSubRegIterator.
On Thu, Aug 30, 2012 at 2:30 PM, Sergei Larin <slarin at codeaurora.org> wrote:
> Hello Jakob and everyone,
>
> I am observing an issue with MCRegUnitIterator in my back end, and trying
> to reverse
2011 May 18
2
[LLVMdev] access array problem
Thank you, Duncan.
I rewrote the code, please help check why it still does not work:
//declare global variable
const Type *IntTy = Type::getInt32Ty(M.getContext());
const Type *ATyC = ArrayType::get(Type::getInt64Ty(M.getContext()), 1);
GlobalVariable *CounterSize = new GlobalVariable(M, ATyC, false,
GlobalValue::InternalLinkage,