similar to: [LLVMdev] How does the memory of MachineInstr objects are managed?

In my ISA, some registers are write-only. These registers serve as output ports, writing to these registers will output the values to an external device. They cannot be read. So their live intervals should not be joined with any other registers. The only way I know to do this is defining several instruction 'templates' for an opcode (of course automatically generated by a script) similar

Didn't SparcV9 backend implement list scheduling? 2005/12/16, Chris Lattner <sabre at nondot.org>: > On Thu, 15 Dec 2005, thean kiat sew wrote: > > I am planning to use list scheduling on LLVM instructions. > > Any recommendation on how to start ? As in which codes in LLVM that I need > > to look at. > > We don't currently have a list scheduler in the

On Tue, 13 Dec 2005, Tzu-Chien Chiu wrote: > In my ISA, some registers are write-only. These registers serve as > output ports, writing to these registers will output the values to an > external device. They cannot be read. So their live intervals should > not be joined with any other registers. Ok. Since they are not really registers in the sense that LLVM is used to, I

The automated tests seems not run periodically. Some builds are even broken (http://llvm.cs.uiuc.edu/testresults/X86-niobe/), and some failed (http://llvm.cs.uiuc.edu/testresults/SparcV9/). Will there be another automated test be scheduled before the next release? On 11/10/05, Bill Wendling <isanbard at gmail.com> wrote: > Frequently releasing software can be a good thing. Especially

2005/12/13, Chris Lattner <sabre at nondot.org>: > > For example, this a code snippet for the file generated by the TableGen tool: > ... > > Somewhere in my code, I have to write: > > unsigned opcode = MI->getOpcode(); // MachineInstr* > > if (CMPfaaaa == opcode || > > CMPfaaar == opcode || > > CMPfaara == opcode || > > ...

2005/12/13, Chris Lattner <sabre at nondot.org>: > On Tue, 13 Dec 2005, Tzu-Chien Chiu wrote: > > > In my ISA, some registers are write-only. These registers serve as > > output ports, writing to these registers will output the values to an > > external device. They cannot be read. So their live intervals should > > not be joined with any other registers. >

LiveInterval.cpp. // that v is live at i'. In this implementation intervals can have holes, // i.e. an interval might look like [1,20), [50,65), [1000,1001). Each // individual range is represented as an instance of LiveRange, and the whole // interval is represented as an instance of LiveInterval. What cause these holes? -- Tzu-Chien Chiu - XGI Technology, Inc. URL:

Dear all: To write a compiler for Microsoft Direct3D shaders from our hardware, I have a program which translates the Direct3D shader assembly to LLVM assembly. I added several intrinsics for this purpose. It's a vector ISA and has some special instructions like: * rcp (reciprocal) * frc (the fractional portion of each input component) * dp4 (dot product) * exp (exponential) * max, min These

The BGL (Boost Graph Library) defines tie(), which is exactly what the tie() defined in STLExtras.h. The header files of GBL use boost::tie(), and other boost libraries use boost::tie() too. How to resolve the ambiguity for compiler? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

I don't understand the following code snippet in LiveIntervalAnalysis.cpp. Why changing the type of the opreand from a virtual register to a machine register? The register number (reg) is still a virtual register index (>1024). bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { // perform a final pass over the instructions and compute spill // weights, coalesce

2005/7/23, Chris Lattner <sabre at nondot.org>: > > What does a 'read only' register mean? Is it a constant (e.g. returns > 1.0)? Otherwise, how can it be a useful value? Yes, it's a constant register. Because the instruction cannot contain an immediate value, a constant value may be stored in a constant register, and it's defined _before_ the program starts by

I though LiveVariables may be invalidated by LiveIntervals, but it's declared not: void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved<LiveVariables>(); AU.addRequired<LiveVariables>(); ... LiveInterval may coalesce virtual registers and remove identity moves instructions: bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {

Frequently releasing software can be a good thing. Especially when it gets to a point where you have a stable CVS version and many new features/bug fixes. -bw On 10/11/05, Chris Lattner <sabre at nondot.org> wrote: > > Hi All, > > It has been entirely too long since the last release, and we have plenty > of goodies for a very solid release. Do people find releases useful,

Hi All, I am planning to use list scheduling on LLVM instructions. Any recommendation on how to start ? As in which codes in LLVM that I need to look at. Since I am still a newbie, any readings recommended? :) Thanks a lot for the help. Regards, Kiat -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Thu, 15 Dec 2005, thean kiat sew wrote: > I am planning to use list scheduling on LLVM instructions. > Any recommendation on how to start ? As in which codes in LLVM that I need > to look at. We don't currently have a list scheduler in the target-independent code generator, but we do have the infrastructure needed to implement one. Check out the

On Thu, 15 Dec 2005, Tzu-Chien Chiu wrote: > To write a compiler for Microsoft Direct3D shaders from our hardware, > I have a program which translates the Direct3D shader assembly to LLVM > assembly. I added several intrinsics for this purpose. > It's a vector ISA and has some special instructions like: > * rcp (reciprocal) > * frc (the fractional portion of each input

One of my pass requires LiveIntervals to build the interference graph, because LiveVariables do not provide an interface to iterate through all viritual registers. But LiveIntervalAnalysis.h is not in "include/llvm/CodeGen", so I have to either include it by: #include "../../llvm/lib/CodeGen/LiveIntervalAnalysis.h" or point my project include path to

All registers in my hardware are 4-element vector registers (128-bit). Some are floating point registers, and the others are integer registers. I typedef two packed classes: [4 x float] and [4 x int], and add an enum 'packed' to MVT::ValueType (ValuesTypes.h). I declared all 'RegisterClass'es to be 'packed' (first argument of RegisterClass): def GeneralPurposeRC :

On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote: > 2005/7/23, Chris Lattner <sabre at nondot.org>: >> What does a 'read only' register mean? Is it a constant (e.g. returns >> 1.0)? Otherwise, how can it be a useful value? > > Yes, it's a constant register. > > Because the instruction cannot contain an immediate value, a constant > value may be stored in

Hi, everyone. I' have three set of registers - read-only regs, general purpose regs (read and write), and write-only regs. How should I partition them into different RegisterClasses so that I can easy define the instruction? All RegisterClasses must be mutally exclusive. That is, a register can only be in a RegisterClass. Otherwise TableGen will raise an error message. def