Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] LLVM-TV web page link is broken?"
2005 Sep 19
0
[LLVMdev] LLVM-TV web page link is broken?
On Mon, 19 Sep 2005, Tzu-Chien Chiu wrote:
> http://llvm.cs.uiuc.edu/~gaeke/llvm-tv
It looks like Brian removed his directory. Brian, do you still have a
copy of that page that we can point people to?
-Chris
--
http://nondot.org/sabre/
http://llvm.org/
2005 Sep 19
2
[LLVMdev] LLVM-TV web page link is broken?
Sorry, I don't personally have any of that stuff anymore -- I seem
to recall that page didn't have a whole lot on it, though. I think
Misha has messed around with llvm-tv more recently than I have. If
you really want that particular page, it looks like you can get (a
version of) it from the Internet Archive...
http://web.archive.org/web/20041102220954/llvm.cs.uiuc.edu/~gaeke/llvm-tv/
2005 Sep 22
3
[LLVMdev] name collision - llvm::tie and boost::tie
The BGL (Boost Graph Library) defines tie(), which is exactly what the
tie() defined in STLExtras.h.
The header files of GBL use boost::tie(), and other boost libraries
use boost::tie() too.
How to resolve the ambiguity for compiler?
--
Tzu-Chien Chiu,
3D Graphics Hardware Architect
<URL:http://www.csie.nctu.edu.tw/~jwchiu>
2005 Sep 07
4
[LLVMdev] LiveIntervals, replace register with representative register?
I don't understand the following code snippet in LiveIntervalAnalysis.cpp.
Why changing the type of the opreand from a virtual register to a
machine register? The register number (reg) is still a virtual
register index (>1024).
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
// perform a final pass over the instructions and compute spill
// weights, coalesce
2005 Sep 07
3
[LLVMdev] LiveIntervals invalidates LiveVariables?
I though LiveVariables may be invalidated by LiveIntervals, but it's
declared not:
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
{
AU.addPreserved<LiveVariables>();
AU.addRequired<LiveVariables>();
...
LiveInterval may coalesce virtual registers and remove identity moves
instructions:
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
2005 Sep 05
3
[LLVMdev] dependence analyzer for machine code?
why there is no general dependency analysis for the "machin code"?
perhaps it's because the instruction scheduling is only implemented
for sparcv9?
i am going to implement a dependency analysis pass for machine code
block. the result will be returned in a boost graph
(http://www.boost.org/libs/graph/doc/table_of_contents.html).
just to check if it has already been implemented. it
2005 Sep 22
3
[LLVMdev] name collision - llvm::tie and boost::tie
On 22/09/05, Bill Wendling <isanbard at gmail.com> wrote:
> Couldn't you state the explicit namespaces. So not using "using
> namespace llvm" and instead prefix all calls with "llvm::"?
The header files in boost do not use fully-qualified tie(). I probably
should not modify them. But my .cpp file #include them.
I hope I could "using namespace" boost
2005 Jul 27
3
[LLVMdev] How to define complicated instruction in TableGen (Direct3D shader instruction)
Each register is a 4-component (namely, r, g, b, a) vector register.
They are actually defined as llvm packed [4xfloat].
The instruction:
add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz
Explaination:
'.a' is a writemask. only the specified component will be update
'.xxyy' and '.zzzz' are swizzle masks, specify the component
permutation, simliar to the Intel SSE permutation
2005 Sep 05
2
[LLVMdev] Pass is not automatically registered
I am not sure if my problem is similar to:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2003-December/000715.html
It seems that the constructor of the static global pass object isn't called:
lib/CodeGen/DependenceAnalyzer.cpp:
static RegisterAnalysis<DependenceAnalyzer> X("depana", "Dependence Analysis");
I traced into struct RegisterAnalysis ctor, but my pass
2005 Jul 23
3
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/23, Chris Lattner <sabre at nondot.org>:
>
> What does a 'read only' register mean? Is it a constant (e.g. returns
> 1.0)? Otherwise, how can it be a useful value?
Yes, it's a constant register.
Because the instruction cannot contain an immediate value, a constant
value may be stored in a constant register, and it's defined _before_
the program starts by
2005 Dec 13
3
[LLVMdev] The live interval of write-only registers
In my ISA, some registers are write-only. These registers serve as
output ports, writing to these registers will output the values to an
external device. They cannot be read. So their live intervals should
not be joined with any other registers.
The only way I know to do this is defining several instruction
'templates' for an opcode (of course automatically generated by a
script) similar
2005 Jul 26
1
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/26, Chris Lattner <sabre at nondot.org>:
> Tzu-Chien Chiu wrote:
> > The same problem exists when there are two types of costant registers,
> > floating point and integer, and each is declared 'packed' ([4xfloat]
> > and [4xint]). The instruction selector doesn't know which instruction
> > it should produce because the newly defined MVT type
2005 Dec 13
2
[LLVMdev] The live interval of write-only registers
2005/12/13, Chris Lattner <sabre at nondot.org>:
> > For example, this a code snippet for the file generated by the TableGen tool:
> ...
> > Somewhere in my code, I have to write:
> > unsigned opcode = MI->getOpcode(); // MachineInstr*
> > if (CMPfaaaa == opcode ||
> > CMPfaaar == opcode ||
> > CMPfaara == opcode ||
> > ...
2005 Dec 16
1
[LLVMdev] List Scheduling on LLVM Instructions
Didn't SparcV9 backend implement list scheduling?
2005/12/16, Chris Lattner <sabre at nondot.org>:
> On Thu, 15 Dec 2005, thean kiat sew wrote:
> > I am planning to use list scheduling on LLVM instructions.
> > Any recommendation on how to start ? As in which codes in LLVM that I need
> > to look at.
>
> We don't currently have a list scheduler in the
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
All registers in my hardware are 4-element vector registers (128-bit).
Some are floating point registers, and the others are integer
registers.
I typedef two packed classes: [4 x float] and [4 x int], and add an
enum 'packed' to MVT::ValueType (ValuesTypes.h).
I declared all 'RegisterClass'es to be 'packed' (first argument of
RegisterClass):
def GeneralPurposeRC :
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
Hi, everyone.
I' have three set of registers - read-only regs, general purpose regs
(read and write), and write-only regs. How should I partition them
into different RegisterClasses so that I can easy define the
instruction?
All RegisterClasses must be mutally exclusive. That is, a register can
only be in a RegisterClass. Otherwise TableGen will raise an error
message.
def
2005 Sep 19
0
[LLVMdev] LLVM-TV web page link is broken?
On Mon, 19 Sep 2005, Brian R. Gaeke wrote:
> Sorry, I don't personally have any of that stuff anymore -- I seem
> to recall that page didn't have a whole lot on it, though. I think
> Misha has messed around with llvm-tv more recently than I have. If
> you really want that particular page, it looks like you can get (a
> version of) it from the Internet Archive...
>
>
2005 Sep 27
1
[LLVMdev] How does the memory of MachineInstr objects are managed?
A question about how the memory of object in LLVM are managed.
I dived in some source files but still don't have any idea how the
memory of MachineInstr object are managed. It doesn't look like
reference counting.
I'm writing an instruction scheudling code, the new order of
MachineInstr* in a MachineBasicBlock is stored in a "schedule". All
MachineInstr* in
2005 Sep 20
2
[LLVMdev] Requiring LiveIntervals
One of my pass requires LiveIntervals to build the interference graph,
because LiveVariables do not provide an interface to iterate through
all viritual registers. But LiveIntervalAnalysis.h is not in
"include/llvm/CodeGen", so I have to either include it by:
#include "../../llvm/lib/CodeGen/LiveIntervalAnalysis.h"
or point my project include path to
2005 Jul 25
2
[LLVMdev] How to partition registers into different RegisterClass?
Thanks, I think it can solve my problem.
But please allow me to explain the hardware in detail. Hope there is
more elegant way to solve it.
The hardware is a "stream processor". That is, It processes samples
one by one. Each sample is associated with several 128-bit
four-element vector registers, namely:
* input registers - the attributes of the sample, the values of the
registers