similar to: [LLVMdev] dependence analyzer for machine code?

On Mon, 2005-09-05 at 14:45 +0800, Tzu-Chien Chiu wrote: > why there is no general dependency analysis for the "machin code"? > perhaps it's because the instruction scheduling is only implemented > for sparcv9? Most backends use the SelectionDAG infastructure to do this kind of thing. (Simplifying things a bit) Each basic block is selected to a DAG based IR. Then

On Sep 5, 2005, at 10:21 AM, Andrew Lenharth wrote: > On Mon, 2005-09-05 at 14:45 +0800, Tzu-Chien Chiu wrote: > >> why there is no general dependency analysis for the "machin code"? >> perhaps it's because the instruction scheduling is only implemented >> for sparcv9? >> > > Most backends use the SelectionDAG infastructure to do this kind of >

I was searching for the code could be factored out for a dependency analyzer. The one written by Tanya for SparcV9. The machine code dependency is necessary for some architecture which the (efficient) instruction scheduling could not be possible without the register allocation is done first. For example, the VLIW machines (most DSP's are). For an efficient instruction scheduling, the

Didn't SparcV9 backend implement list scheduling? 2005/12/16, Chris Lattner <sabre at nondot.org>: > On Thu, 15 Dec 2005, thean kiat sew wrote: > > I am planning to use list scheduling on LLVM instructions. > > Any recommendation on how to start ? As in which codes in LLVM that I need > > to look at. > > We don't currently have a list scheduler in the

A question about how the memory of object in LLVM are managed. I dived in some source files but still don't have any idea how the memory of MachineInstr object are managed. It doesn't look like reference counting. I'm writing an instruction scheudling code, the new order of MachineInstr* in a MachineBasicBlock is stored in a "schedule". All MachineInstr* in

The automated tests seems not run periodically. Some builds are even broken (http://llvm.cs.uiuc.edu/testresults/X86-niobe/), and some failed (http://llvm.cs.uiuc.edu/testresults/SparcV9/). Will there be another automated test be scheduled before the next release? On 11/10/05, Bill Wendling <isanbard at gmail.com> wrote: > Frequently releasing software can be a good thing. Especially

The BGL (Boost Graph Library) defines tie(), which is exactly what the tie() defined in STLExtras.h. The header files of GBL use boost::tie(), and other boost libraries use boost::tie() too. How to resolve the ambiguity for compiler? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

I want to enumerate all the operands of a machine instruction, but the iterator seems to skip everything except virtual registers. Is this by design? MachineInstr.h <code> template<class MITy, class VTy> class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> { void skipToNextVal() { while (i < MI->getNumOperands() && !(

On 08/09/05, Chris Lattner <sabre at nondot.org> wrote: > This code isn't actually replacing the virtual register with a physreg. Then why changing its optype? It makes the assertion fails: MachineOperand& MO = inst.getOperand(n); if (MRegisterInfo::isVirtualRegister(MO.getReg())) { assert(MachineOperand::MO_VirtualRegister == MO.getType()); ... } Is that alright? Some

On 08/09/05, Alkis Evlogimenos <evlogimenos at gmail.com> wrote: > representative register (found using a union find algorithm). Note that > the representative register could be a real register if we ever joined > an interval of a real register with one of a virtual register (and this > real register will be the representative register of the set of > intervals joined

I don't understand the following code snippet in LiveIntervalAnalysis.cpp. Why changing the type of the opreand from a virtual register to a machine register? The register number (reg) is still a virtual register index (>1024). bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { // perform a final pass over the instructions and compute spill // weights, coalesce

Each register is a 4-component (namely, r, g, b, a) vector register. They are actually defined as llvm packed [4xfloat]. The instruction: add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz Explaination: '.a' is a writemask. only the specified component will be update '.xxyy' and '.zzzz' are swizzle masks, specify the component permutation, simliar to the Intel SSE permutation

i'd like to know if there is any plan or existing work to add a Aho's trig language like code generator generator? "...If you are starting a new port, we recommend that you write the instruction selector using the SelectionDAG infrastructure." any other things i should know before i write one? thank you.

http://portal.acm.org/citation.cfm?id=75700 On 4/25/05, Chris Lattner <sabre at nondot.org> wrote: > On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote: > > i'd like to know if there is any plan or existing work to add a Aho's > > trig language like code generator generator? > > Trig is a code generator generator? Is there any documentation for it > available

I though LiveVariables may be invalidated by LiveIntervals, but it's declared not: void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved<LiveVariables>(); AU.addRequired<LiveVariables>(); ... LiveInterval may coalesce virtual registers and remove identity moves instructions: bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {

2005/7/23, Chris Lattner <sabre at nondot.org>: > > What does a 'read only' register mean? Is it a constant (e.g. returns > 1.0)? Otherwise, how can it be a useful value? Yes, it's a constant register. Because the instruction cannot contain an immediate value, a constant value may be stored in a constant register, and it's defined _before_ the program starts by

In my ISA, some registers are write-only. These registers serve as output ports, writing to these registers will output the values to an external device. They cannot be read. So their live intervals should not be joined with any other registers. The only way I know to do this is defining several instruction 'templates' for an opcode (of course automatically generated by a script) similar

national compiler infrastructure - http://www.cs.virginia.edu/nci/ is there any on-going efforts to integrate llvm with other nci projects?

On 22/09/05, Bill Wendling <isanbard at gmail.com> wrote: > Couldn't you state the explicit namespaces. So not using "using > namespace llvm" and instead prefix all calls with "llvm::"? The header files in boost do not use fully-qualified tie(). I probably should not modify them. But my .cpp file #include them. I hope I could "using namespace" boost

i'd like to know what progress you guys have made (not on cvs?). i don't want to re-invent wheels, and the existing many code generator generators. i am evaluating many possbile code generation libraries. at present i give me preferrence to "Prop": http://www.cs.nyu.edu/leunga/www/prop.html and it's portable too. are there any other good library you could recommend?