similar to: [LLVMdev] Anyone is building a DSP-C frontend?

fixed-point number could be stored in LLVM first class integer types. i cannot see the problem now. but to be type-safe, there should be a first class 'fixed'. some llvm extensions required to mapping dsp-c lanaguages could be implemented as qualifiers. 1. _sat qualifier Saturate the result within [0.0, +1.0> or [-1.0,+1.0> (unsigned/singed). sat signed fixed a; sat signed fixed

On Sat, Jun 13, 2015 at 01:08:50PM +0300, Simon Atanasyan wrote: > Hi, > > If you need to control content of output .note section, take a look at > ARMExidxSection, MipsReginfoSection, MipsOptionsSection classes. If > you need to copy sections from input to output, use SDataSection (from > Hexagon) as a reference point. > Hi Simon, Thanks for the reply. I have a few more

On Wed, 31 Aug 2005, Tzu-Chien Chiu wrote: > fixed-point number could be stored in LLVM first class integer types. > i cannot see the problem now. but to be type-safe, there should be a > first class 'fixed'. There is no need. Lowering is fine, in the same way that enums or typedefs are currently lowered to llvm integer types. > some llvm extensions required to mapping

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 This is a snippet of an email I sent to Mark Taylor (who I contacted thru this list) today. I thought I should share this with you... I am the double >> and zero-> typer. > > On the other side, we've developed a new version of our DDS software > > (remember the novell+NT to Linux+openldap+samba migration?) and theyre >

Hello, I use the function 'aggregate' a lot. One small annoyance is that it is necessary to name the factors in the 'by' list to get the names in the resulting data.frame (else, they appear as Group.1, Group.2...etc). For example, I am forced to write: aggregate(y,list(f1=f1,f2=f2),mean) instead of aggregate(y,list(f1,f2),mean) (for two factors with short names, it is not such

Chris, LLVM is an excellent piece of work, LLVM is one of the few project I know that has used the mysterious GCC front-end. I think it will be a great contribution to the community if you could writeup and document how to interface to the GCC front-end data-structures (like LLVM has done). Specifically: a) detail the gcc front-end tree data-structures b) how to go about interfacing to them

I was searching for the code could be factored out for a dependency analyzer. The one written by Tanya for SparcV9. The machine code dependency is necessary for some architecture which the (efficient) instruction scheduling could not be possible without the register allocation is done first. For example, the VLIW machines (most DSP's are). For an efficient instruction scheduling, the

Hi folks, According to the wiki,? it's considered a feature of Dovecot and its ability to support multiple authentication sources that "if the password doesn't match in the first database, it checks the next one". ?) http://wiki.dovecot.org/Authentication/MultipleDatabases I think it's great that Dovecot allows auth sources to be stacked like this, but I am not sold on the

The BGL (Boost Graph Library) defines tie(), which is exactly what the tie() defined in STLExtras.h. The header files of GBL use boost::tie(), and other boost libraries use boost::tie() too. How to resolve the ambiguity for compiler? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

Dear all: To write a compiler for Microsoft Direct3D shaders from our hardware, I have a program which translates the Direct3D shader assembly to LLVM assembly. I added several intrinsics for this purpose. It's a vector ISA and has some special instructions like: * rcp (reciprocal) * frc (the fractional portion of each input component) * dp4 (dot product) * exp (exponential) * max, min These

I don't understand the following code snippet in LiveIntervalAnalysis.cpp. Why changing the type of the opreand from a virtual register to a machine register? The register number (reg) is still a virtual register index (>1024). bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { // perform a final pass over the instructions and compute spill // weights, coalesce

2005/7/26, Chris Lattner <sabre at nondot.org>: > Tzu-Chien Chiu wrote: > > The same problem exists when there are two types of costant registers, > > floating point and integer, and each is declared 'packed' ([4xfloat] > > and [4xint]). The instruction selector doesn't know which instruction > > it should produce because the newly defined MVT type

http://portal.acm.org/citation.cfm?id=75700 On 4/25/05, Chris Lattner <sabre at nondot.org> wrote: > On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote: > > i'd like to know if there is any plan or existing work to add a Aho's > > trig language like code generator generator? > > Trig is a code generator generator? Is there any documentation for it > available

Each register is a 4-component (namely, r, g, b, a) vector register. They are actually defined as llvm packed [4xfloat]. The instruction: add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz Explaination: '.a' is a writemask. only the specified component will be update '.xxyy' and '.zzzz' are swizzle masks, specify the component permutation, simliar to the Intel SSE permutation

I though LiveVariables may be invalidated by LiveIntervals, but it's declared not: void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved<LiveVariables>(); AU.addRequired<LiveVariables>(); ... LiveInterval may coalesce virtual registers and remove identity moves instructions: bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {

why there is no general dependency analysis for the "machin code"? perhaps it's because the instruction scheduling is only implemented for sparcv9? i am going to implement a dependency analysis pass for machine code block. the result will be returned in a boost graph (http://www.boost.org/libs/graph/doc/table_of_contents.html). just to check if it has already been implemented. it

Actually the problems that Tzu-Chien Chiu are encountering are similar to what should be done for generating SSE code in the X86 backend and also other SIMD instruction sets. I think LLVM neeeds to add instructions for permuting components, extracting and injecting elements in packed types. If the architecture has instructions which can do permutations for each instruction (for example

On 22/09/05, Bill Wendling <isanbard at gmail.com> wrote: > Couldn't you state the explicit namespaces. So not using "using > namespace llvm" and instead prefix all calls with "llvm::"? The header files in boost do not use fully-qualified tie(). I probably should not modify them. But my .cpp file #include them. I hope I could "using namespace" boost

2005/7/23, Chris Lattner <sabre at nondot.org>: > > What does a 'read only' register mean? Is it a constant (e.g. returns > 1.0)? Otherwise, how can it be a useful value? Yes, it's a constant register. Because the instruction cannot contain an immediate value, a constant value may be stored in a constant register, and it's defined _before_ the program starts by

i'd like to know what progress you guys have made (not on cvs?). i don't want to re-invent wheels, and the existing many code generator generators. i am evaluating many possbile code generation libraries. at present i give me preferrence to "Prop": http://www.cs.nyu.edu/leunga/www/prop.html and it's portable too. are there any other good library you could recommend?