similar to: [LLVMdev] How to partition registers into different RegisterClass?

On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote: > I' have three set of registers - read-only regs, general purpose regs > (read and write), and write-only regs. How should I partition them > into different RegisterClasses so that I can easy define the > instruction? [snip] > def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest, >

All registers in my hardware are 4-element vector registers (128-bit). Some are floating point registers, and the others are integer registers. I typedef two packed classes: [4 x float] and [4 x int], and add an enum 'packed' to MVT::ValueType (ValuesTypes.h). I declared all 'RegisterClass'es to be 'packed' (first argument of RegisterClass): def GeneralPurposeRC :

On Fri, 22 Jul 2005, Tzu-Chien Chiu wrote: > All registers in my hardware are 4-element vector registers (128-bit). > Some are floating point registers, and the others are integer > registers. > > I typedef two packed classes: [4 x float] and [4 x int], and add an > enum 'packed' to MVT::ValueType (ValuesTypes.h). > > I declared all 'RegisterClass'es to be

On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote: > 2005/7/23, Chris Lattner <sabre at nondot.org>: >> What does a 'read only' register mean? Is it a constant (e.g. returns >> 1.0)? Otherwise, how can it be a useful value? > > Yes, it's a constant register. > > Because the instruction cannot contain an immediate value, a constant > value may be stored in

2005/7/23, Chris Lattner <sabre at nondot.org>: > > What does a 'read only' register mean? Is it a constant (e.g. returns > 1.0)? Otherwise, how can it be a useful value? Yes, it's a constant register. Because the instruction cannot contain an immediate value, a constant value may be stored in a constant register, and it's defined _before_ the program starts by

Thanks, I think it can solve my problem. But please allow me to explain the hardware in detail. Hope there is more elegant way to solve it. The hardware is a "stream processor". That is, It processes samples one by one. Each sample is associated with several 128-bit four-element vector registers, namely: * input registers - the attributes of the sample, the values of the registers

On Mon, 25 Jul 2005, Tzu-Chien Chiu wrote: > But please allow me to explain the hardware in detail. Hope there is > more elegant way to solve it. Sounds good! > The hardware is a "stream processor". That is, It processes samples > one by one. Each sample is associated with several 128-bit > four-element vector registers, namely: > > * input registers - the

Hello Jianzhou, On Sat, Aug 14, 2010 at 8:25 PM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: > Hi, > > Does 2.8 release plan to change anything in Ocaml bindings? > http://llvm.org/docs/ReleaseNotes.html#whatsnew does not list any > relevant features. I usually wait until around nowish before a release to sync llvm-c and the ocaml bindings. I'll start the process.

Hi, Does 2.8 release plan to change anything in Ocaml bindings? http://llvm.org/docs/ReleaseNotes.html#whatsnew does not list any relevant features. 2.7 added 'operand' that can access each operand from a value. external operand : llvalue -> int -> llvalue = "llvm_operand" Does this binding also expose a primitive to return how many operands a given value has? I need

On Feb 13, 2007, at 11:27 AM, Evan Cheng wrote: >> >> Thanks Evan, >> >> I had tried something like this, but ran into some problems. >> >> llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1478: failed assertion >> `MVT::isVector(VT) && "Cannot promote this load!"' >> >> and >> >>

On Feb 12, 2007, at 1:41 AM, Christopher Lamb wrote: > > selector refused to select certain ops (specifically stores) for some > instructions when the operand type wasn't the first type for the > register class. After some digging around I seem to have solved the > problem by creating bitconvert patterns between the types in the > register class like the following: > >

Hi All, I'm working on a back end for an architecture that makes use of multi- typed register classes. def MR: RegisterClass<"namespace", [type1, type2, ... ], ... > When running some preliminary tests I found that the instruction selector refused to select certain ops (specifically stores) for some instructions when the operand type wasn't the first type for the

> > Thanks Evan, > > I had tried something like this, but ran into some problems. > > llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1478: failed assertion > `MVT::isVector(VT) && "Cannot promote this load!"' > > and > > llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1766: failed assertion > `MVT::isVector(VT) && "Unknown legal

2005/7/24, Chris Lattner <sabre at nondot.org>: > Ah, ok. In that case, you want to put all of the registers in one register > file, and not make the constant register allocatable (e.g. see > X86RegisterInfo.td, and note how the register classes include EBP and ESP, > but do not register allocate them (through the definition of > allocation_order_end()). > > -Chris

On Sat, 13 May 2006, Vladimir Prus wrote: > I'm porting some existing code of mine to CVS HEAD, and don't understand > something about new RegisterClass TableGen definition: > > class RegisterClass<string namespace, list<ValueType> regTypes,........ > { > ..... > string Namespace = namespace; > > What is this "namespace"

Hi, I've come across a problem while working on an LLVM backend for a new target architecture. This architecture has two single-ported register files. Each instruction can only read one operand from each register file, but can write to either. I tried implementing it naïvely in TableGen with two definitions per instruction, so I had: def AllRegs : RegisterClass< ... (add interleave

Excellent, I've implemented my own PBQP register allocator and solved the issue very painlessly. Now onto those more interesting problems! Thanks for your suggestion, Fraser On Fri, Oct 5, 2012 at 9:26 AM, Gergö Barany <gergo at complang.tuwien.ac.at>wrote: > On Thu, Oct 04, 2012 at 16:20:53 +0100, Fraser Cormack wrote: > > This architecture has two single-ported register

Thank you for the answer. What is the main reason of allowing this inconsistency in the td file? I guess that's because of the "some" distinction between the writeback and non-writeback versions. Is there any benefit from the inconsistency by using GRP in .td file and freezing lr and pc during register allocation in writeback version? Thanks, Junbum On May 23, 2013, at 11:51 AM,

when i use the RegisterClass(&WndClass); under wine the call fails. I'm using it to sub class the button class. Does wine not support this? Interdynamics Web Page : http://www.interdynamics.com

On 19 January 2014 10:19, Thomson <lilotom at gmail.com> wrote: > The blow snippet in target.td shows the regList in RegisterClass is typed as > dag. Why not make it a simple list, such as list<Register>? I don't know about the original reason, but these days we have a few operators in use to make constructing those sets easier which would be much harder to do for lists.