similar to: [LLVMdev] llvm fits in the national compiler infrastructure (nci)?

i don't know the status of nci, but suif/suif2 development and publication is very active. it's will be great if there are tools to transform llvm ir and suif ir to each other. acutally, i didn't use suif but llvm just because suif cannot be compiled by visual studio.net (but visual studio 6). On 5/10/05, Vladimir Prus <ghost at cs.msu.su> wrote: > On Tuesday 10 May 2005

On Tuesday 10 May 2005 15:12, Tzu-Chien Chiu wrote: > national compiler infrastructure - http://www.cs.virginia.edu/nci/ "Last updated on February 4, 1998." and mailing list archives dont work. Does not seems like a live project. - Volodya

The BGL (Boost Graph Library) defines tie(), which is exactly what the tie() defined in STLExtras.h. The header files of GBL use boost::tie(), and other boost libraries use boost::tie() too. How to resolve the ambiguity for compiler? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

I don't understand the following code snippet in LiveIntervalAnalysis.cpp. Why changing the type of the opreand from a virtual register to a machine register? The register number (reg) is still a virtual register index (>1024). bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { // perform a final pass over the instructions and compute spill // weights, coalesce

Each register is a 4-component (namely, r, g, b, a) vector register. They are actually defined as llvm packed [4xfloat]. The instruction: add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz Explaination: '.a' is a writemask. only the specified component will be update '.xxyy' and '.zzzz' are swizzle masks, specify the component permutation, simliar to the Intel SSE permutation

i'd like to know if there is any plan or existing work to add a Aho's trig language like code generator generator? "...If you are starting a new port, we recommend that you write the instruction selector using the SelectionDAG infrastructure." any other things i should know before i write one? thank you.

http://portal.acm.org/citation.cfm?id=75700 On 4/25/05, Chris Lattner <sabre at nondot.org> wrote: > On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote: > > i'd like to know if there is any plan or existing work to add a Aho's > > trig language like code generator generator? > > Trig is a code generator generator? Is there any documentation for it > available

why there is no general dependency analysis for the "machin code"? perhaps it's because the instruction scheduling is only implemented for sparcv9? i am going to implement a dependency analysis pass for machine code block. the result will be returned in a boost graph (http://www.boost.org/libs/graph/doc/table_of_contents.html). just to check if it has already been implemented. it

I though LiveVariables may be invalidated by LiveIntervals, but it's declared not: void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved<LiveVariables>(); AU.addRequired<LiveVariables>(); ... LiveInterval may coalesce virtual registers and remove identity moves instructions: bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {

2005/7/23, Chris Lattner <sabre at nondot.org>: > > What does a 'read only' register mean? Is it a constant (e.g. returns > 1.0)? Otherwise, how can it be a useful value? Yes, it's a constant register. Because the instruction cannot contain an immediate value, a constant value may be stored in a constant register, and it's defined _before_ the program starts by

In my ISA, some registers are write-only. These registers serve as output ports, writing to these registers will output the values to an external device. They cannot be read. So their live intervals should not be joined with any other registers. The only way I know to do this is defining several instruction 'templates' for an opcode (of course automatically generated by a script) similar

On 22/09/05, Bill Wendling <isanbard at gmail.com> wrote: > Couldn't you state the explicit namespaces. So not using "using > namespace llvm" and instead prefix all calls with "llvm::"? The header files in boost do not use fully-qualified tie(). I probably should not modify them. But my .cpp file #include them. I hope I could "using namespace" boost

i'd like to know what progress you guys have made (not on cvs?). i don't want to re-invent wheels, and the existing many code generator generators. i am evaluating many possbile code generation libraries. at present i give me preferrence to "Prop": http://www.cs.nyu.edu/leunga/www/prop.html and it's portable too. are there any other good library you could recommend?

Actually the problems that Tzu-Chien Chiu are encountering are similar to what should be done for generating SSE code in the X86 backend and also other SIMD instruction sets. I think LLVM neeeds to add instructions for permuting components, extracting and injecting elements in packed types. If the architecture has instructions which can do permutations for each instruction (for example

I am not sure if my problem is similar to: http://lists.cs.uiuc.edu/pipermail/llvmdev/2003-December/000715.html It seems that the constructor of the static global pass object isn't called: lib/CodeGen/DependenceAnalyzer.cpp: static RegisterAnalysis<DependenceAnalyzer> X("depana", "Dependence Analysis"); I traced into struct RegisterAnalysis ctor, but my pass

On Tue, 13 Dec 2005, Tzu-Chien Chiu wrote: > In my ISA, some registers are write-only. These registers serve as > output ports, writing to these registers will output the values to an > external device. They cannot be read. So their live intervals should > not be joined with any other registers. Ok. Since they are not really registers in the sense that LLVM is used to, I

On Mon, 2005-09-05 at 14:45 +0800, Tzu-Chien Chiu wrote: > why there is no general dependency analysis for the "machin code"? > perhaps it's because the instruction scheduling is only implemented > for sparcv9? Most backends use the SelectionDAG infastructure to do this kind of thing. (Simplifying things a bit) Each basic block is selected to a DAG based IR. Then

All registers in my hardware are 4-element vector registers (128-bit). Some are floating point registers, and the others are integer registers. I typedef two packed classes: [4 x float] and [4 x int], and add an enum 'packed' to MVT::ValueType (ValuesTypes.h). I declared all 'RegisterClass'es to be 'packed' (first argument of RegisterClass): def GeneralPurposeRC :

2005/7/26, Chris Lattner <sabre at nondot.org>: > Tzu-Chien Chiu wrote: > > The same problem exists when there are two types of costant registers, > > floating point and integer, and each is declared 'packed' ([4xfloat] > > and [4xint]). The instruction selector doesn't know which instruction > > it should produce because the newly defined MVT type

Thanks, I think it can solve my problem. But please allow me to explain the hardware in detail. Hope there is more elegant way to solve it. The hardware is a "stream processor". That is, It processes samples one by one. Each sample is associated with several 128-bit four-element vector registers, namely: * input registers - the attributes of the sample, the values of the registers