similar to: [LLVMdev] calling conventions and inlining

On Sun, 8 May 2005, Markus F.X.J. Oberhumer wrote: > Chris Lattner wrote: >> On Sat, 7 May 2005, Markus F.X.J. Oberhumer wrote: >>> but looking at the disassembly suggests that this might mainly be an issue >>> of x86 codegen, which is rather young as compared to other compilers. >> If you're testing on X86, I would be strongly suspious of the X86 backend,

On Sat, 7 May 2005, Markus F.X.J. Oberhumer wrote: > Chris Lattner wrote: >> On Sat, 7 May 2005, Markus F.X.J. Oberhumer wrote: >> >>> As I've just seen that there are some things going on w.r.t the long >>> needed implementation of calling conventions, may I also ask if it's >>> possible to address inlining at the same moment (i.e. attributes

On Wed, 2005-09-07 at 18:24 +0800, Tzu-Chien Chiu wrote: > I though LiveVariables may be invalidated by LiveIntervals, but it's > declared not: > > void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const > { > AU.addPreserved<LiveVariables>(); > AU.addRequired<LiveVariables>(); > ... > > LiveInterval may coalesce virtual registers and

On Sat, 7 May 2005, Markus F.X.J. Oberhumer wrote: > As I've just seen that there are some things going on w.r.t the long needed > implementation of calling conventions, may I also ask if it's possible to > address inlining at the same moment (i.e. attributes always_inline and > noinline, but maybe LLVM wants a finer grained level here) ? They really are different issues.

Are you suggesting that we have "always_inline" and "never_inline" keywoards that can be attributed to functions? If so, why do you want this level of control? What's wrong with the current inlining pass? Reid. On Sat, 2005-05-07 at 20:34 +0200, Markus F.X.J. Oberhumer wrote: > As I've just seen that there are some things going on w.r.t the long > needed

On Sat, 7 May 2005, Markus F.X.J. Oberhumer wrote: > Actually I feel that the current state of the art of inlining is where > register allocation has been about 10 years ago. It's pretty fine for most > things, but back then I remember writing code like "register const char *p > __asm__("%esi");" where just adding the explicit __asm__ boosted performance

On Wed, 2005-09-07 at 15:09 +0800, Tzu-Chien Chiu wrote: > I don't understand the following code snippet in LiveIntervalAnalysis.cpp. > > Why changing the type of the opreand from a virtual register to a > machine register? The register number (reg) is still a virtual > register index (>1024). > > > bool LiveIntervals::runOnMachineFunction(MachineFunction &fn)

On 4/3/07, David Greene <greened at obbligato.org> wrote: > > Toward a better register allocator, I'm attempting to understand > the dataflow information available to the allocator. > > What's the difference between LiveInterval information and LiveVariable > information? If a LiveInterval is based on a linear ordering of > the machine instructions, isn't it

On Thursday 10 February 2005 21:47, Markus F.X.J. Oberhumer wrote: > In order to get more familiar with the llvm sources I've recently > decided to try to add support for the always_inline and noline function > attributes. I believe it is better to let the compiler decide when or not to inline a function. Most of the times a developer goes overboard with inlining and ends up with a

On 08/09/05, Alkis Evlogimenos <evlogimenos at gmail.com> wrote: > to those coalesced registers, it is logical that noone will ever query > the liveness of those registers (unless there is a bug somewhere in the Indeed the coalesced registers may logically not be queried since they do not appear in any operand list of the machine code, but the VarInfo::DefInst in VirtRegInfo of the

There is one case where inlining/not-inlining affects correctness. A function which uses alloca() will behave differently in the two cases. You can argue one shouldn't write code like this, but it is legal. Chris Lattner wrote: > On Sat, 7 May 2005, Markus F.X.J. Oberhumer wrote: > >> I see that you are objecting explicit inline control. >> >> The main problem is

I though LiveVariables may be invalidated by LiveIntervals, but it's declared not: void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved<LiveVariables>(); AU.addRequired<LiveVariables>(); ... LiveInterval may coalesce virtual registers and remove identity moves instructions: bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {

On Sat, 7 May 2005, Markus F.X.J. Oberhumer wrote: > I see that you are objecting explicit inline control. > > The main problem is that inlining is absolutely crucial for some > "modern" programming styles. E.g. we use a huge collection of small C++ > template classes and template metaclasses, most of which have very > trivial and limited functionality (think of it

LiveVariables gives you something like liveness analysis: where each variable is alive, that is, across each basic blocks, where it is defined, and where it is killed. LiveIntervals gives you a linear representation of the variables as a set of intervals. Yes, it handle holes in the live ranges. There is a very nice description of these analysis and related data structures here:

Toward a better register allocator, I'm attempting to understand the dataflow information available to the allocator. What's the difference between LiveInterval information and LiveVariable information? If a LiveInterval is based on a linear ordering of the machine instructions, isn't it rather conservative in nature? Let's say I have a typical diamond CFG: A

On Thu, May 06, 2004 at 04:06:27PM +0200, Finn S Andersen wrote: > Chris Lattner wrote: > > >I think that we should switch to C constants in this case. Can you try > >#include <math.h> and use HUGE_VAL instead? > > > It works: > > [finna at coplin11 ~/test]$ cat tst.cpp > #include <limits> > #include <iostream> > #include

I don't understand the following code snippet in LiveIntervalAnalysis.cpp. Why changing the type of the opreand from a virtual register to a machine register? The register number (reg) is still a virtual register index (>1024). bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { // perform a final pass over the instructions and compute spill // weights, coalesce

Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level O2, not O0. The probable reason of this error is that no LiveInterval information for newly MBB which is used by Register Allocation. And, LiveIntervals depend

On 08/09/05, Alkis Evlogimenos <evlogimenos at gmail.com> wrote: > representative register (found using a union find algorithm). Note that > the representative register could be a real register if we ever joined > an interval of a real register with one of a virtual register (and this > real register will be the representative register of the set of > intervals joined

On Thu, 2004-07-01 at 09:26, Vladimir Prus wrote: > I've tried to implement the isMoveInstr method from TargetInstrInfo class, and > the register allocator immediately started to crash, in: > > #4 0x40e88787 in llvm::LiveIntervals::joinIntervals (this=0x80630b0) > at ../lib/CodeGen/LiveIntervals.cpp:493 > 493 assert(r2iA != r2iMap_.end()); >