Displaying 20 results from an estimated 4000 matches similar to: "[LLVMdev] trig language-like code generator generator"
2005 Apr 24
0
[LLVMdev] trig language-like code generator generator
On Sun, Apr 24, 2005 at 07:15:03PM +0800, Tzu-Chien Chiu wrote:
> i'd like to know if there is any plan or existing work to add a Aho's
> trig language like code generator generator?
I'm not aware of either the trig language code generator nor any work to
implement it in LLVM.
> "...If you are starting a new port, we recommend that you write the
> instruction
2005 Apr 24
2
[LLVMdev] trig language-like code generator generator
http://portal.acm.org/citation.cfm?id=75700
On 4/25/05, Chris Lattner <sabre at nondot.org> wrote:
> On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote:
> > i'd like to know if there is any plan or existing work to add a Aho's
> > trig language like code generator generator?
>
> Trig is a code generator generator? Is there any documentation for it
> available
2005 Apr 25
4
[LLVMdev] trig language-like code generator generator
i'd like to know what progress you guys have made (not on cvs?).
i don't want to re-invent wheels, and the existing many code generator
generators. i am evaluating many possbile code generation libraries.
at present i give me preferrence to "Prop":
http://www.cs.nyu.edu/leunga/www/prop.html
and it's portable too.
are there any other good library you could recommend?
2005 Apr 24
0
[LLVMdev] trig language-like code generator generator
On Mon, 25 Apr 2005, Tzu-Chien Chiu wrote:
> http://portal.acm.org/citation.cfm?id=75700
Oh, tWig. :) Yes, tree pattern matching is exactly the direction we are
heading. We are slowly making the code generators more and more
automatically generated as time goes on. The SelectionDAG infrastructure
is mean to support exactly this (perform Tree or DAG pattern matching on
the optimized DAG
2005 Apr 25
0
[LLVMdev] trig language-like code generator generator
On Mon, 25 Apr 2005, Tzu-Chien Chiu wrote:
> i'd like to know what progress you guys have made (not on cvs?).
Everything is in CVS. Noone is currently working on automating the
pattern matching generator process yet. Before doing that, there are a
few changes we want to make to the SelectionDAG interface. In particular,
right now, the selection process basically works like this:
#1.
2005 Apr 25
1
[LLVMdev] trig language-like code generator generator
the proposed architecture (chris) doesn't seem to attack the phase
ordering problem. through having independent instruction selection,
instruction scheduling, and register allocation phases faciliate a
modular design, but i believe the phase-coupled code generator
generator high quality code on many architectures. espeically in the
embedded system like a media/dsp processors with very limited
2005 Apr 24
0
[LLVMdev] trig language-like code generator generator
On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote:
> i'd like to know if there is any plan or existing work to add a Aho's
> trig language like code generator generator?
Trig is a code generator generator? Is there any documentation for it
available anywhere?
-Chris
> "...If you are starting a new port, we recommend that you write the
> instruction selector using the
2005 May 06
1
[LLVMdev] initialize 'dag' variable and interpret asmstring in tablegen .td file
The macro $src, $dest used in Instruction::AsmString must be
"declared" in Instruction::OperandList, right?
$$ has special meaning?
On 5/6/05, Chris Lattner <sabre at nondot.org> wrote:
> On Fri, 6 May 2005, Tzu-Chien Chiu wrote:
> > llvm/lib/Target/X86/X86InstrInfo.td:
> > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string
> >
2005 May 06
2
[LLVMdev] initialize 'dag' variable and interpret asmstring in tablegen .td file
llvm/lib/Target/X86/X86InstrInfo.td:
class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string
AsmStr> : Instruction {
....
dag OperandList = ops;
string AsmString = AsmStr;
}
def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
"mov{l} {$src, $dst|$dst, $src}">;
I cannot find any document on initializing the
2005 Sep 22
3
[LLVMdev] name collision - llvm::tie and boost::tie
The BGL (Boost Graph Library) defines tie(), which is exactly what the
tie() defined in STLExtras.h.
The header files of GBL use boost::tie(), and other boost libraries
use boost::tie() too.
How to resolve the ambiguity for compiler?
--
Tzu-Chien Chiu,
3D Graphics Hardware Architect
<URL:http://www.csie.nctu.edu.tw/~jwchiu>
2005 May 06
0
[LLVMdev] initialize 'dag' variable and interpret asmstring in tablegen .td file
On Fri, 6 May 2005, Tzu-Chien Chiu wrote:
> llvm/lib/Target/X86/X86InstrInfo.td:
> class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string
> AsmStr> : Instruction {
> ....
> dag OperandList = ops;
> string AsmString = AsmStr;
> }
>
> def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
> "mov{l}
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
Hi, everyone.
I' have three set of registers - read-only regs, general purpose regs
(read and write), and write-only regs. How should I partition them
into different RegisterClasses so that I can easy define the
instruction?
All RegisterClasses must be mutally exclusive. That is, a register can
only be in a RegisterClass. Otherwise TableGen will raise an error
message.
def
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
All registers in my hardware are 4-element vector registers (128-bit).
Some are floating point registers, and the others are integer
registers.
I typedef two packed classes: [4 x float] and [4 x int], and add an
enum 'packed' to MVT::ValueType (ValuesTypes.h).
I declared all 'RegisterClass'es to be 'packed' (first argument of
RegisterClass):
def GeneralPurposeRC :
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote:
> I' have three set of registers - read-only regs, general purpose regs
> (read and write), and write-only regs. How should I partition them
> into different RegisterClasses so that I can easy define the
> instruction?
[snip]
> def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
>
2005 Sep 07
4
[LLVMdev] LiveIntervals, replace register with representative register?
I don't understand the following code snippet in LiveIntervalAnalysis.cpp.
Why changing the type of the opreand from a virtual register to a
machine register? The register number (reg) is still a virtual
register index (>1024).
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
// perform a final pass over the instructions and compute spill
// weights, coalesce
2005 Jul 27
3
[LLVMdev] How to define complicated instruction in TableGen (Direct3D shader instruction)
Each register is a 4-component (namely, r, g, b, a) vector register.
They are actually defined as llvm packed [4xfloat].
The instruction:
add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz
Explaination:
'.a' is a writemask. only the specified component will be update
'.xxyy' and '.zzzz' are swizzle masks, specify the component
permutation, simliar to the Intel SSE permutation
2005 Sep 05
3
[LLVMdev] dependence analyzer for machine code?
why there is no general dependency analysis for the "machin code"?
perhaps it's because the instruction scheduling is only implemented
for sparcv9?
i am going to implement a dependency analysis pass for machine code
block. the result will be returned in a boost graph
(http://www.boost.org/libs/graph/doc/table_of_contents.html).
just to check if it has already been implemented. it
2005 Sep 07
3
[LLVMdev] LiveIntervals invalidates LiveVariables?
I though LiveVariables may be invalidated by LiveIntervals, but it's
declared not:
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
{
AU.addPreserved<LiveVariables>();
AU.addRequired<LiveVariables>();
...
LiveInterval may coalesce virtual registers and remove identity moves
instructions:
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
2005 Jul 23
3
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/23, Chris Lattner <sabre at nondot.org>:
>
> What does a 'read only' register mean? Is it a constant (e.g. returns
> 1.0)? Otherwise, how can it be a useful value?
Yes, it's a constant register.
Because the instruction cannot contain an immediate value, a constant
value may be stored in a constant register, and it's defined _before_
the program starts by
2005 Dec 13
3
[LLVMdev] The live interval of write-only registers
In my ISA, some registers are write-only. These registers serve as
output ports, writing to these registers will output the values to an
external device. They cannot be read. So their live intervals should
not be joined with any other registers.
The only way I know to do this is defining several instruction
'templates' for an opcode (of course automatically generated by a
script) similar