similar to: [LLVMdev] Question about MachineFunction Pass

On Tue, 19 Oct 2004, Zhang Qiuyu wrote: > I wrote a machinefunction pass to try to see what's going on. Does it > mean that it is target machine dependent pass, like x86? However, after > compile it, I found there wasnot command option I registered. I used > regular way to do it like RegisterOpt <...> X("... ", "... "), but I > cannot see the optimized

Hello, llvmers. Could someone explain me a little about the opt tool? I am having problems to load a MachineFunctionPass using opt. I have this pass: #include "llvm/Pass.h" #include "llvm/Function.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include <iostream> using namespace llvm; namespace { struct MacFoo : public MachineFunctionPass { virtual

On Mon, 1 May 2006, Fernando Magno Quintao Pereira wrote: > Hello, llvmers. Could someone explain me a little about the opt tool? I am > having problems to load a MachineFunctionPass using opt. I have this pass: MachineFunctionPass's cannot be used as part of opt, they can only be used as part of LLC. Further, you have to explicitly modify the target you are interested in to add it

Hi All ! I have some windows-maked dll (xxx.dll for example). I want to use it on my Linux machine in my Java application. For this purpose I wrote a small wrapper around the xxx.dll by using winelib library and make it as libxxx.dll.so. Now I need load this library in my jvm (by using System.loadLibrary("xxx.dll"); ) but when I try to call any function from it I got

Hi everyone, I am a LLVM newbie. I need to write a machinefunction pass for my project. This should be an analyzer of the machine code to do some profiling. I have written a couple of function passes for front end, but it seems they are completely different. I searched through forum and llvm documents, but couldn't find anything useful or questions were unanswered. Can anyone reference me to

I am trying to set up somthing so I can dial into my asterisk box, and have it behave as a modem bank. Is there anything like that already, or am I going to have to write my own. I checked googls and found no leads, but thought I would ask here before I tried writing my own, just to make sure I wasnot reinventing the wheel. Thank you in advance for any responses. -Chris

I believe I'm seeing a bug in lpxelinux.0 6.03-pre17 but I need some advice on how to isolate and troubleshoot this. (I can't try pre18 at the moment, but did try 4.07 and 5.10 and saw similar behavior, also with pxelinux.0, so although I'll give pre18 a try soon, some isolation/troubleshooting advice will be a good education no matter what.) To get to our PXE-launched tools from

Hi all, I am experimenting with samba 4. I have existing data on NTFS partition and want to share them via samba. But I have problems with permissions (ACL). There is an option: ntvfs handler that tells how mapping of permissions between unix and windows world shall behave. But there is lack of documentation. So I tried posix, simiple but in either case I wasnot able to write even set permissions

Hey Andy > One easy pattern to follow is to register the option during pass initialization with all the convenient flags and parameters, but refer to a globally defined option storage that enforces the singleton and provides visibility. As long as pass initialization happens before parseCommandLine, usage should be consistent. > > Strawman: > > cl::optval<bool> MyOption; //

Op 2014-07-01 om 22:55 schreef Gene Cumm: > On Jul 1, 2014 10:37 PM, "Alexander Perlis" wrote: > > > > I believe I'm seeing a bug in lpxelinux.0 6.03-pre17 but I need some > > advice on how to isolate and troubleshoot this. (I can't try pre18 > > at the moment, but did try 4.07 and 5.10 and saw similar behavior, > > also with pxelinux.0, so

On 08/27/2010 11:05, Dale Johannesen wrote: >>>> Function only has on BB. Is this wrong that it has both >>>> TCRETURNri64 and RET in one BB? >>> >>> Yes, that is wrong. The reason emitEpilogue isn't lowering the >>> TCRETURN is that it doesn't see it, it only sees the RET. The real >>> problem will be where that RET is

On Fri, 27 Aug 2004 02:20:34 -0500 (CDT) Chris Lattner <sabre at nondot.org> wrote: > On Thu, 26 Aug 2004, Jeff Cohen wrote: > > > Also, the store into the arrays generates two x86 machine > > instructions: > > > > lea %ECX, DWORD PTR [%ESP + 16] > > mov DWORD PTR [%ECX + <element offset>], %EAX > > > > These can be combined into a

Dear John, Thank you so much for your help. I looked at those documents. Could you kindly answer the following questions: Does it mean that I have to make my own backend target in order to write a machine pass even if I want to run a simple machinefunction pass? for example,if I want my pass to get MIPS instructions as an input, I have to copy all the files from mips target and add a file to it

On 08/27/2010 11:32, Yuri wrote: > As I understand only one of TCRETURNri64 and RET should be created. > I have sources of rev.112200. > > Here is the stack when TCRETURNri64 instruction is created: > #1 0x0000000802c8b4e2 in llvm::MachineFunction::CreateMachineInstr > (this=0x30eb000, TID=@0x803a78940, DL={LineCol = 0, ScopeIdx = 0}, > NoImp=false) at

Dear All, Currently I am trying to inject custom x86-64 assembly into a functions entry basic block. More specifically, I am trying to build assembly in a machine function pass from scratch. While the dumped machine function instruction info displays that %gs will be used, when I perform objdump -d on my executable I am see that %gs is replaced by %ebp? Why is this happening? I know it probably

Hi, In the following function, i hope to save my simulated data into the "result" dataset, but why the final "result" dataset seems not to be generated. #Function simdata<-function (nsim) { result<-matrix(NA,nrow=nsim,ncol=2) colnames(result)<-c("x","y") for (i in 1:nsim) { set.seed(i) result[i,]<- cbind(runif(1),runif(1)) }

Thank you so much. That helped alot. Fami On Wed, Nov 4, 2015 at 9:40 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/3/15 7:54 PM, fateme Hoseini wrote: > > Dear John, > Thank you so much for your help. I looked at those documents. Could you > kindly answer the following questions: > > Does it mean that I have to make my own backend target in order to write

If I have an instruction which has many register and immediate operands, what's the difference between these two implementations to define the instruction in TableGen *.td file? (1) Similar to what has been done to complex X86 addressing mode. A single 32-bit immediate (i32) encodes how to add many MachineOperands to the MachineInstr object (With the help of functions in X86InstrBuilder.h).

I've looked at the last 6 months on the list and did not find any reference on how to static compile of rsync. I looked at the ./configure --help with no luck. I'm on solaris 2.8 using gcc 4.1.1. when I run thru the process (./configure; make; make install) and run ldd rsync, I get a list of 10 or so libxxx.so.n. I'm compiling rsync-3.0.0. I need to distribute the rsync pgm to 25

Hi, So, I run my pass in X86 target with llc command and it printed out "hello****". Now I am trying to do the same pass for ARM target. So I did exactly what I did for X86 as mentioned in my previous posts. When I run the following command: llc -march=arm test.ll -o test nothing prints out. I did the same for MIPS target too and I got no result. Can anyone tell me what I'm doing