similar to: [LLVMdev] Register allocator segfault

Displaying 12 results from an estimated 12 matches similar to: "[LLVMdev] Register allocator segfault"

2005 May 17
2
[LLVMdev] Register Allocation problem
Ok, i'm having a problem with understanding the allocating of registers. I've written in the "addPassesToEmitAssembly()" the passes to create the assembly code, as in the PowerPC example. I'ved tried filling up as much of the code in <Target>RegisterInfo.cpp (Register/Frame code) to handle writing and reading from stack. The allocation method I used was
2005 May 17
0
[LLVMdev] Register Allocation problem
On Mon, May 16, 2005 at 05:15:30PM -0700, John Cortes wrote: > If I use any of the regalloc parameters (local, ...) I get an error in > the LiveVariable.cpp file, in the part that I think cheaks for dead > code because a Variable didn't have a defined Instance to a Machine > instruction. > > " llc: LiveVariables.cpp:86: void >
2007 Aug 16
0
[LLVMdev] Changing basic blocks
Hi all, A week agoo I sent an email about reordering instruction in basicblocks. And ... I was able to do it. I guess so, at least. Now when compiling my test program, llc dumps: -- llc: /home/mentat/llvm_work/llvm/lib/CodeGen/LiveVariables.cpp:155: void llvm::LiveVariables::HandleVirtRegUse(llvm::LiveVariables::VarInfo&, llvm::MachineBasicBlock*, llvm::MachineInstr*): Assertion
2007 Aug 10
2
[LLVMdev] Changing basic blocks
For adding the nop: TII->insertNoop(*BB, BB->end()); 2007/8/9, Chris Lattner <sabre at nondot.org>: > > On Thu, 9 Aug 2007, [ISO-8859-1] Emílio Wuerges wrote: > > I too believe it should not be complicated. > > But I was not being able to do it. > > Finally, after some thinking (and tinkering), this worked like a charm: > > > > MachineInstr* mi =
2019 Mar 25
2
[IndVars] Rewriting exit value of SCEV add expressions
Hi, I found issues with INDVARS <-> LSR passes interactions after https://reviews.llvm.org/rL346397. There were two main changes in this commit: 1. Previously we were propagating SCEV add expressions even if DefInst of exit value has hard uses inside the loop. After rL346397 we forbid propagation of SCEV add expressions if DefInst of exit value has hard use inside the loop. 2. Previously
2005 Sep 07
1
[LLVMdev] LiveIntervals invalidates LiveVariables?
On 08/09/05, Alkis Evlogimenos <evlogimenos at gmail.com> wrote: > to those coalesced registers, it is logical that noone will ever query > the liveness of those registers (unless there is a bug somewhere in the Indeed the coalesced registers may logically not be queried since they do not appear in any operand list of the machine code, but the VarInfo::DefInst in VirtRegInfo of the
2009 Nov 20
2
[LLVMdev] llc barfing
I was playing with optimization switches to llc to see how fast I could get it to compile but it keeps barfing. Tinkering indicates that llc barfs particularly when -tailcallopt is given in combination with other flags. For example, without -tailcallopt works in a couple of ways: $ llc -O0 -f aout.bc -o aout.s $ llc -O0 --regalloc=local -f aout.bc -o aout.s But fails with -tailcallopt with
2005 Sep 07
0
[LLVMdev] LiveIntervals invalidates LiveVariables?
On Wed, 2005-09-07 at 18:24 +0800, Tzu-Chien Chiu wrote: > I though LiveVariables may be invalidated by LiveIntervals, but it's > declared not: > > void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const > { > AU.addPreserved<LiveVariables>(); > AU.addRequired<LiveVariables>(); > ... > > LiveInterval may coalesce virtual registers and
2020 Jun 26
2
How to implement load/store for vector predicate register
Hi, I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands. If I use virtual registers, do I need to mark them as "early clobber"? I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend. What is the effect of marking a
2005 Sep 07
3
[LLVMdev] LiveIntervals invalidates LiveVariables?
I though LiveVariables may be invalidated by LiveIntervals, but it's declared not: void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved<LiveVariables>(); AU.addRequired<LiveVariables>(); ... LiveInterval may coalesce virtual registers and remove identity moves instructions: bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
2011 Aug 24
1
[LLVMdev] proposal: add macro expansion of for-loop to TableGen
Hi folks, TableGen provides sufficiently rich syntax for expressing target instruction set. Nevertheless, when I wrote the PTX backend, I observed that some redundancy in TableGen can be further eliminated through macro expansion of for-loops. The semantics of a for-loop is expanding the for-loop body, and so it is equivalent to manually unroll the loop (see example #1). I believe the for-loop
2017 May 17
2
Machine instruction verifier pass
- Please do not add any more uses of the LiveVariables pass! It is deprecated and only kept around for one last pass that isn't converted. All new code should use LiveIntervalAnalysis! - Kill flags are optional: If they are present they must be correct, but it is legal to have a value die without having a kill flag on the operand. So often a simple fix is to clear out the kill flags from