similar to: [LLVMdev] Minor tblgen patch

The docs for MachineFunction::create method have a couple of nits: // The next three methods are used to construct, destruct, and retrieve the // MachineFunction object for the given method. // // construct() -- Allocates and initializes for a given method and target // get() -- Returns a handle to the object. // This should not be called before

On Wednesday 04 May 2005 18:34, Chris Lattner wrote: > On Wed, 4 May 2005, Vladimir Prus wrote: > > %tmp.aux = cast bool %tmp.24 to int > > %tmp.x = xor int %tmp.aux, 1 ; negates tmp.24 > > %tmp.xx = cast int %tmp.x to bool > > %tmp.y = or bool %tmp.xx, %tmp.24 ; will be always true > > br bool %tmp.y,

Misha Brukman wrote: > LLVM Machine code is in SSA. This explains quite a lot. I though it's possible to just reduce convert phis into copy instructions in predecessors -- all of which will have the same destination register. > gets you two definitions of r. So we have machine PHI nodes merge the > two possible values into one for result of r. These phis get removed > after

Hello, I'm considering a possibility of writing an llvm backend for my research uses. Unfortunately, I can't find much information on how do to it. I more or less understood now the C backend is implemented, but for real backend I'd need at least register allocation. I beleive there's already register allocator in LLVM and I would like to reuse it if possible. The question is

Could anybody quickly explain why PHI nodes instructions are necessary in machine code? And why the code in LiveVariables.cpp which looks at those PHI nodes (line 249 and below) is necessary. The reason I'm asking is that I try to support 64-bit comparison and I do it by generating code like: // if high1 cond high2: goto operand0 // if high1 reverse_cond high2:

On Wed, 18 Aug 2004, Henrik Bach wrote: > I think I've found the error: > > The Buffer contains: include "../Target.td" and length is 23. > The file that tablegen is looking for is therefore: "../Target.td". > > However, in the assertion you assert an empty buffer and that is not what > you want, I suppose. If you change line 114 to != instead ==, then

Hi I've been investigating which characters that cause troubles: Length = 23 WhatsInBuffer=include "../Target.td" assert=false tblgen: Assertion failed: "Buffer[Length-1] == '"'", file FileLexer.l, line 128 idx hex char 0 69 i 1 6E n 2 63 c 3 6C l 4 75 u 5 64 d 6 65 e 7 20 8 22 " 9 2E . 10 2E . 11 2F / 12 54 T 13 61 a 14 72 r 15 67 g 16 65 e 17 74 t 18

Hi Chris >From: Chris Lattner <sabre at nondot.org> >Date: Fri, 13 Aug 2004 16:23:53 -0500 (CDT) > >On Fri, 13 Aug 2004, Henrik Bach wrote: > > > I got this error: > > ------------------------------- > > gmake[3]: Entering directory `/usr/local/src/llvm/lib/Target/X86' > > Building X86.td register information header with tblgen > > tblgen:

On Tue, Aug 17, 2004 at 09:39:23PM -0500, Chris Lattner wrote: > > The next problem, on my system (Interix - you remember - Hey, some > > LLVM program is working :O ), is however, that it cannot find the > > ../Target.td file. At the moment I see some more bugs luring ahead > > in the TableGen code. More on that later. > > I'm sure this is because you hacked the

Hi, looking at the fresh CVS state I see: class Register<string n> : RegisterBase<n> { list<RegisterBase> Aliases = []; } while previously the Register class did not require any parameters. The change log is just: * Target.td: Revamp the Register class, and allow the use of the RegisterGroup class to specify aliases directly in register definitions. and I

Evan Cheng wrote: > > On Dec 3, 2007, at 12:53 PM, Vladimir Prus wrote: > >> >> Suppose I have a target that does not have register+constant >> addressing mode. Then, I have DAG like: >> >> (store ..., (frameindex)) >> >> Targets like SPARC have the following patterns to catch this: >> >> def ADDRri : ComplexPattern<i32, 2,

Suppose I have a target that does not have register+constant addressing mode. Then, I have DAG like: (store ..., (frameindex)) Targets like SPARC have the following patterns to catch this: def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; def STri : F3_2<3, 0b000100, (outs), (ins MEMri:$addr, IntRegs:$src),

Hi *, to decide in which namespace tablegen should place the instruction-enum, tablegen iterates over CodeGenTarget instructions until it finds an Instruction with a namespace other than "TargetInstInfo".. but this is wrong, as internal Instructions now use "TargetOpcode" as Namespace.. As Instructions are a map, it is only by chance which is the first instruction it finds -

On Thu, May 05, 2005 at 09:47:50AM +0400, Vladimir Prus wrote: > > Actually, the -instcombine pass already does this. Please try it > > out and let me know if it doesn't do what you want. > > It does work! For some reason, I was assuming that running 'opt' > without arguments would run some "reasonable" set of optimizations, > while in reality, it

On Dec 3, 2007, at 12:53 PM, Vladimir Prus wrote: > > Suppose I have a target that does not have register+constant > addressing mode. Then, I have DAG like: > > (store ..., (frameindex)) > > Targets like SPARC have the following patterns to catch this: > > def ADDRri : ComplexPattern<i32, 2, > "SelectADDRri", [frameindex], []>; > def STri :

On Fri, 9 Jul 2004, Vladimir Prus wrote: > Misha Brukman wrote: > > > LLVM Machine code is in SSA. > > This explains quite a lot. I though it's possible to just reduce convert phis > into copy instructions in predecessors -- all of which will have the same > destination register. There are algorithms for eliminating PHI nodes, but they aren't quite so simple.

PHI nodes within machine code were originally used by the Sparc back-end but they turned out not to be necessary. Instead, LLVM phis are lowered to copy instructions in the machine code (I believe this happens just after instruction selection). As far as I know, the machine PHI nodes are not used by the x86 back-end and you shouldn't need them if you insert the right copies. --Vikram

Chris Lattner wrote: > On Tue, 22 Jun 2004, Vladimir Prus wrote: > > First, I attach two files -- LLVM asm and the asm for my target. The > > problem with assembler is: on line 171 it uses register gr2, which is > > copied from gr6 above, on line 161. The only predecessor of this basic > > block is jump on line 90. The problem is that gr6 is not initialized in > >

Hi! When I go to http://llvm.cs.uiuc.edu/doxygen/annotated.html and click on link for, say, "llvm::Module", I've told that the target page does not exist. Same happens for llvm::Value, and in fact everything under "llvm" namespace. Any idea what's wrong? - Volodya

Vladimir Prus wrote: > Vladimir Prus wrote: > > The above-mentioned test contains this: > > > > long B53 = - (1LL << 53); > > > > strictly speaking, this is not correct code. The C standard says about > > shift: "if the value of the first operator is ... or greater than ... the > > width of the promoted left operand, the behaviour is