similar to: [Bug 15252] New: X crashes on start with Geforce 7000M VGA

Hi, This is really basic block level pass. It is no difference what is level, problem is the same. After fixing for asm parser, assembler syntax is no more valid for backend, without processing with asm parser. May be it will be solution to process inline asm on insn printer level to remove syntax fixes. But just switch it off without lto will make compiler do less job P.S. sorry for dup,

Hi, Imagine that your backend has valid asm instruction written like this: "%x mnem %y, %z" And user puts it as inline assembler: __asm__ ("%x mnem %y, %z"); It can not be parsed with current llvm asm parser, because it starts with % (moreover it has mnemonic in second place) Say you written pass, that makes it "mnem %x, %y, %z". Now this guy can be parsed, but

Hi, In LTO we have AsmParser that process inline assembler instructions to MCInst and I want to fix some inline assembler in order to conform its rules (do not start with non-identifier and so on) because asm syntax of our backend allows some incompatible patterns. In order to do this I am adding IR-level target-specific pass. But those fixes shall not be applied when there is no AsmParser later

After update I have got this: samba-tool drs kcc -Uadm2 -d 9 INFO: Current debug levels: all: 9 tdb: 9 printdrivers: 9 lanman: 9 smb: 9 rpc_parse: 9 rpc_srv: 9 rpc_cli: 9 passdb: 9 sam: 9 auth: 9 winbind: 9 vfs: 9 idmap: 9 quota: 9 acls: 9 locking: 9 msdfs: 9 dmapi: 9 registry: 9 scavenger: 9 dns: 9 ldb: 9 tevent: 9 auth_audit: 9

Hi, Default register allocator tries to reuse the same registers over and over again even if register file have a plenty of registers to use. This creates parasite false dependencies and makes scheduling less effective. How to instruct allocator (may be override some virtual function in mine backend?) that it is profitable to use maximum number of available registers with minimal dependencies?

Hi, I regularly have errors (kernel: dst cache overflow) and crash of a firewall under Linux 2.6.17 and the route patch from Julian Anastasov. With rtstat I see that the route cache size increases regularly without never decreasing. I have this parameters: fw:/proc/sys/net/ipv4/route# grep . * error_burst:1250 error_cost:250 gc_elasticity:15 gc_interval:60 gc_min_interval:0

Hi, I want to enable some target-specific functionality only if current build is 2nd LTO stage (i.e. optimizer called from plugin). What is best and recommended way to do it? --- With best regards, Konstantin

Hi, Working on private backend, based on llvm-3.7 Inside lib/Transforms/InstCombine/InstCombineCompares.cpp there is attempt to optimize fabs: if (F->getIntrinsicID() == Intrinsic::fabs || ... switch (I.getPredicate()) { ... case FCmpInst::FCMP_OGT: return new FCmpInst(FCmpInst::FCMP_ONE, CI->getArgOperand(0), RHSC); But CI->getArgOperand(0)

Hi, Thanks for pointing direction. As far, as I understand by reversing, logic, that I want to overwrite is digged into: lib/MC/MCSectionELF.cpp MCSectionELF::PrintSwitchToSection if (ShouldOmitSectionDirective(SectionName, MAI)) { OS << '\t' << getSectionName() << '\n'; return; } // otherwise print ".section" directive and then section

Hi, I am debugging private backend and faced interesting problem: sometimes spill hoisting creates double stores. (some output from -debug-only=regalloc). First hoisting: Checking redundant spills for 0 at 16r in %vreg19 [16r,144B:0)[144B,240B:1)[240B,280r:2)[296r,416B:3)[416B,456r:4)[472r,592B:5) 0 at 16r 1 at 144B-phi 2 at 240B-phi 3 at 296r 4 at 416B-phi 5 at 472r Merged to stack int: SS#0

Hi, I tried using the nouveau driver that comes latest with Fedora Rawhide (xorg-x11-drv-nouveau-0.0.10-1.20080311git460cb26) on my HP Pavilion dv2000 laptop with a GeForce 7150M (PCI 10de:0531) but couldn't even get the server up. The server spit out the following log. Could someone tell me how to get things working? Or even if I should file a bug? Xorg.0.log: X.Org X Server 1.4.99.901

On Thu, Mar 15, 2012 at 11:00:54AM +0400, Konstantin Vladimirov wrote: > Hi, > > Thanks for pointing direction. As far, as I understand by reversing, > logic, that I want to overwrite is digged into: > > lib/MC/MCSectionELF.cpp > > MCSectionELF::PrintSwitchToSection > > if (ShouldOmitSectionDirective(SectionName, MAI)) { > OS << '\t'

On 2/16/2016 8:44 AM, Konstantin Vladimirov via llvm-dev wrote: > > CI->getArgOperand(0) returns operand with type (double*) rather then > double, because in our ABI doubles are passed via memory. The LLVM intrinsics in the LLVM IR must conform to whatever the IR's requirements are. That means that even in the case of your backend, the arguments to the intrinsic must be doubles,

Hi, In GCC there is one useful option -dp (or -dP for more verbose output) to annotate assembler with instruction patterns, that was used when assembler was generated. For example: double test(long long s) { return s; } gcc -S -dp -O0 test.c test: .LFB0: .cfi_startproc pushq %rbp # 18 *pushdi2_rex64/1 [length = 1] .cfi_def_cfa_offset 16 movq %rsp, %rbp # 19 *movdi_1_rex64/2

On 02.03.2012, at 09:20, Konstantin Vladimirov wrote: > Hi, > > In GCC there is one useful option -dp (or -dP for more verbose output) > to annotate assembler with instruction patterns, that was used when > assembler was generated. For example: The internal "-mllvm -show-mc-inst" option is probably as close as you can get. $ clang -S -O0 test.c -mllvm -show-mc-inst -o

Hi, I have a situation where router has to see hosts  in multiple vlans with the same IP address The test scenario is : --------------------- |  eth0 |     br0   | &lt;-------&gt; eth1.25 | eth1.26 | eth1.27 --------------------- eth0 = Internet br0 = Lan 192.168.100.1/24 host 1= 192.168.100.11/24 eth1.25 host 2= 192.168.100.12/24 eth1.26 I need br0 to see all hosts in all vlans

Hi, I have noticed that the Windows 7 machines that I have recently installed and joined to our domain take about 40 seconds on average to go from sign in to the desktop displaying. I can't find any explanation for the delay. When the machine are in a work group they login very quickly and the XP machines login at a normal rate. I have searched and not found any articles that are relevant.

We have a router with two external and one internal interfaces and it doesn''t work as we''d like to. We need it to route all the trafic through one of the external interfaces and to access a few networks through the other. Currently it seems that all the packets with source address from the inernal network are routed correctly. The problem is with the packets that originate from

John, I had raised the matter ten years ago, and I was told that the topic was already very^3 old https://stat.ethz.ch/pipermail/r-devel/2006-September/042684.html there is some discussion on its origin and also a declaration of intents to change the default behaviour, which, unfortunately, remained a declaration. I agree that R could do better here, let's hope in less than ten years

I was wondering if it would make sense to change the default behavior of the following: summary(15555L) ## Min. 1st Qu. Median Mean 3rd Qu. Max. ## 15560 15560 15560 15560 15560 15560 summary.default on numeric values rounds values (not just presentation) to getOption("digits")-3L (or four) digits by default, making those values surprising and less suitable for