Displaying 20 results from an estimated 20000 matches similar to: "[LLVMdev] New TableGen document"
2014 Mar 18
4
[LLVMdev] TableGen docs
Hi folks,
It took a while, but I finally have some bandwidth to look at this.
I've been reading the two existing TableGen documents:
http://llvm.org/docs/TableGenFundamentals.html
http://llvm.org/docs/TableGen/LangRef.html
the first is linked from the index, but LangRef is not (though it has
some remains in the metadata). I'm wondering what's the relationship
between them two.
My
2012 Aug 06
0
[LLVMdev] Tablegen foreach
I think a multiclass may be a better fit for what you are trying to
do. In fact, this is the canonical example for multiclasses:
<http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions-and-instances>.
--Sean Silva
On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> I’m trying to find examples of the foreach pattern being used in
2012 Aug 06
0
[LLVMdev] Tablegen foreach
I believe multiclasses can be nested. Could that help you reduce the
duplication?
--Sean Silva
On Mon, Aug 6, 2012 at 2:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this:
>
> multiclass
2012 Aug 06
2
[LLVMdev] Tablegen foreach
That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this:
multiclass instmcRegImm<...> {
def rr: inst<...>;
def ri: inst<...>;
def ir: inst<...>;
def ii: inst<...>;
}
multiclass instmc<...> {
defm i8 : instmcRegImm<...>;
^-- repeat for 15
2012 May 07
1
[LLVMdev] TableGen backend API refactoring.
tl;dr: is anyone opposed to making the interface to a TableGen backend be:
void MyBackend(RecordKeeper &, raw_ostream & /* maybe some other args, per
backend's needs */);
??
Currently, this is the "interface" for a TableGen backend:
struct TableGenBackend {
virtual void anchor();
virtual ~TableGenBackend() {}
// run - All TableGen backends should implement the run
2012 Aug 06
2
[LLVMdev] Tablegen foreach
I'm trying to find examples of the foreach pattern being used in tablegen files.
The problem I am trying to solve is to simplify the amount of tablegen code I have to produce because each operand of an instruction can be a register or a literal.
So for binary, we have 4 instructions, ternary, 8, and quaternary 16 combinations.
Instead of writing all the combinations out, I'd like to use
2013 Sep 24
0
[LLVMdev] request for tutorial
(Sorry about the wall of text, it ended up as a brain dump of a bunch of
backend-related documentation that I know about/have bookmarked in the
past. Hopefully there's something useful in there.)
If you haven't stumbled across them already, these might be helpful:
http://llvm.org/devmtg/2009-10/Korobeynikov_BackendTutorial.pdf
http://jonathan2251.github.io/lbd/
2005 May 06
0
[LLVMdev] initialize 'dag' variable and interpret asmstring in tablegen .td file
On Fri, 6 May 2005, Tzu-Chien Chiu wrote:
> llvm/lib/Target/X86/X86InstrInfo.td:
> class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string
> AsmStr> : Instruction {
> ....
> dag OperandList = ops;
> string AsmString = AsmStr;
> }
>
> def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
> "mov{l}
2005 May 06
1
[LLVMdev] initialize 'dag' variable and interpret asmstring in tablegen .td file
The macro $src, $dest used in Instruction::AsmString must be
"declared" in Instruction::OperandList, right?
$$ has special meaning?
On 5/6/05, Chris Lattner <sabre at nondot.org> wrote:
> On Fri, 6 May 2005, Tzu-Chien Chiu wrote:
> > llvm/lib/Target/X86/X86InstrInfo.td:
> > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string
> >
2011 Oct 06
0
[LLVMdev] TableGen and Greenspun
Jakob Stoklund Olesen <jolesen at apple.com> writes:
> The TableGen language seems to be growing Lisp macros from two
> different directions.
>
> Che-Liang Chiou added a preprocessor with for loops, and David Greene
> added multidefs.
>
> It seems that some kind of macro facility is needed, perhaps we should
> discuss what it is supposed to look like?
Don't
2011 Mar 09
0
[LLVMdev] Question about TableGen when adding LLVM Backend.
On Mar 9, 2011, at 2:13 PM, Lu Mitnick wrote:
> Hello all,
>
> I have some question about usage of TableGen when adding a new LLVM Backend. There are three place to use TableGen in basic steps of document "Writing an LLVM Compiler
> Backend":
>
> 2. Describe the register set of the target. Use "TableGen" to generate code for register definition, register
2011 Mar 09
2
[LLVMdev] Question about TableGen when adding LLVM Backend.
Hello all,
I have some question about usage of TableGen when adding a new LLVM Backend.
There are three place to use TableGen in basic steps of document "Writing an
LLVM Compiler
Backend":
2. Describe the register set of the target. Use "TableGen" to generate code
for register definition, register aliases, and register classes from a
target-specific RegisterInfo.td input
2011 Mar 10
2
[LLVMdev] Question about TableGen when adding LLVM Backend.
Hello Jakob,
Is this means that TableGen execution is handled in Makefile. Porting
programmer doesn't need to execute TableGen by hand?
thanks
2011/3/10 Jakob Stoklund Olesen <stoklund at 2pi.dk>
>
> On Mar 9, 2011, at 2:13 PM, Lu Mitnick wrote:
>
> > Hello all,
> >
> > I have some question about usage of TableGen when adding a new LLVM
> Backend. There
2012 May 23
1
[LLVMdev] tblgen for generation of Haskell bindings to LLVM intrinsics
I want to generate Haskell bindings to LLVM intrinsics. In a first attempt I
wrote a little parser that reads IntrinsicsX86.td and outputs a Haskell module.
E.g. the definition
def int_x86_avx_max_ps_256 : GCCBuiltin<"__builtin_ia32_maxps256">,
Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty,
llvm_v8f32_ty], [IntrNoMem]>;
is turned into
2020 Sep 07
2
Document TableGen classes with Doxygen?
Let's say I wanted to start writing a document on how to create a backend for TableGen. Such a document is suggested in "TableGen Backends." Should I describe the classes that are available to the backend in detail, or should I spend time updating the Doxygen comments in the class header files and simply present an overview in the document?
2009 Dec 14
1
[LLVMdev] TableGen Fundamentals
Hello LLVM,
Following the documentation for the TableGen Fundamentals, I found the below
error when I tried to run tblgen. Also, I got a similar error when I tried
-class=Instruction option. How I can generate the missed file?
Thanks in advance,
Juan Carlos
******************************************************************************************
***@ubuntu:~/llvm/lib/Target/X86$ tblgen X86.td
2016 Nov 18
2
Tablegen doc bug?
Hello,
http://llvm.org/docs/TableGen/LangIntro.html says I can use octal integer value (indicated by a leading 0).
In fact the number is converted to decimal.
With best regards,
Romick.
2018 Apr 24
0
RFC: general machine-parsable backend for TableGen (e.g. JSON)
Hi Simon,
that makes sense to me. Please add me on any reviews when you're done.
Cheers,
Nicolai
On 23.04.2018 14:08, Simon Tatham via llvm-dev wrote:
> Hello llvm-dev,
>
> Would there be any interest in adding a back end to TableGen to produce output in a general-purpose but machine-parsable format?
>
> At the moment, TableGen has two kinds of output option. The -gen-foo
2018 Apr 23
3
RFC: general machine-parsable backend for TableGen (e.g. JSON)
Hello llvm-dev,
Would there be any interest in adding a back end to TableGen to produce output in a general-purpose but machine-parsable format?
At the moment, TableGen has two kinds of output option. The -gen-foo options are each tailored to a particular use case; the -print-records option is fully general, but it's difficult to machine-parse, since its output is in the same syntax as the
2011 Oct 07
0
[LLVMdev] Enhancing TableGen
On Oct 7, 2011, at 11:23 AM, David A. Greene wrote:
> Evan Cheng <evan.cheng at apple.com> writes:
>
>> David, we cannot accept the 'multidef' keyword. Please revert it.
>
> Working on it now.
Thanks.
>
>> We appreciate you thinking ahead about MIC, but we are against the
>> massive refactoring and complicated abstraction scheme. We'll never