similar to: [LLVMdev] Problem with `as'

Displaying 20 results from an estimated 300 matches similar to: "[LLVMdev] Problem with `as'"

2016 Feb 09
2
[GVN] same sequence of instructions in if and else branch
There is a phi-node "%phi = phi i64 [%cast1, %if], [%cast2, %else]" in the common successor. The actual control flow is a bit more complex, but there is a common successor block, and %cast1 and %cast2 are the two values that the phi node in the common successor takes. Does the existence of the phi node affect optimization? Thanks, Taewook From: <mats.o.petersson at
2016 Feb 09
2
[GVN] same sequence of instructions in if and else branch
and by "right thing" i mean it can hoist if you want and it can prove it will not extend the live range. Note that VBE (very busy expressions) is a code size optimization only. It does not save time. On Tue, Feb 9, 2016 at 12:26 PM, Daniel Berlin <dberlin at dberlin.org> wrote: > This GVN does not do that, this is correct. It is a very simple GVN. All > phi nodes are
2016 Feb 09
3
[GVN] same sequence of instructions in if and else branch
Hello, I found that GVN doesn't promote identical sequence of instructions in if and else branch to their common predecessors. For example, for the following code snippet pred: … br i1 %cmp, label %if, label %else if: %incdec.ptr.1 = getelementptr inbounds i8, i8* %ptr, i64 1 %cast1 = ptrtoint i8* %incdec.ptr.1 to i64 … else: %incdec.ptr.2 = getelementptr inbounds i8, i8* %ptr,
2011 Oct 22
0
[LLVMdev] Instruction Scheduling Itineraries
On Oct 21, 2011, at 12:15 AM, James Molloy wrote: > Hi Andy, > > Could you describe how this would be done? In the current ARM itineraries > (say C-A9 for example), the superscalar issue stage is modelled as taking 1 > cycle. If it were to take 2 cycles instead, as far as I can tell the hazard > analyser would stall because both FU's would be acquired. > > I would
2010 Feb 22
2
adding infrequent date labels to x-axis
I'm sure there is a clever way to do the following, but I've been unable to find it on this forum or by writing my own functions. I have 8 years worth of weekly data but would like to restrict the labels on the x-axis to months only. I've included the first year's worth of data below. My line of thought has been along these lines
2011 Mar 25
2
"for" loop assistance -
All ? I have an example data frame x lc1 id 43.38812035 85 ga1 47.55710661 85 ga1 47.55710661 85 ga2 47.55710661 85 ga2 51.99211429 85 ga3 51.99211429 85 ga3 51.99211429 95 ga1 54.78449958 95 ga1 54.78449958 95 ga2 54.78449958 95 ga2 56.70201864 95 ga3 56.70201864 95 ga3 56.70201864 105 ga1 59.66361903 105 ga1 59.66361903 105 ga2 61.69573564 105 ga2 61.69573564 105 ga3 61.69573564 105 ga3
2007 Jul 30
1
Module question: resources evaluated once or repeatedly?
I''ve been working up my first puppet module, one that will make Amanda configurations consistently. In general, I''d like the following to happen: - Each Amanda server should make sure all its holding disks are configured properly; this should only happen once per server, per puppetd run. Definitely not on a per-configuration basis. - Each Amanda server should keep its
2005 Aug 22
2
problem building dendrograms to use with heatmap()
Hi, I'm trying to build dendrograms to pass to heatmap(). The dendrograms I build plot properly, but when I pass them to heatmap() I get the error message "row dendrogram ordering gave index of wrong length" (see output log below). I looked in the code of heatmap() and saw that the error was due to a NULL return value from order.dendrogram(), which in turn got a NULL return value
2009 Sep 29
2
[LLVMdev] SoftenSetCCOpernads in LegalizeFloatTypes.cpp
While generating a libcall from floating point comparison, it always assumes that the return type of those libcalls is i32. Why not allow Targets to provide the correct return type? EVT RetVT = MVT::i32; // <-- here SDValue Ops[2] = { LHSInt, RHSInt }; NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl); NewRHS = DAG.getConstant(0, RetVT); CCCode =
2009 Apr 24
2
[PATCH] Blackfin: cleanup astat/cc/hardware loop asm clobbers
Most asm statements clobber ASTAT bits (shifts, maxes, etc...) but do declare the register as clobbered. Same thing with CC in a few places. Some places make an attempt at clobbering some hardware loop registers, but it's very incomplete compared with how many asm statements actually use hardware loops. Signed-off-by: Mike Frysinger <vapier at gentoo.org> --- libspeex/bfin.h
2009 Sep 29
0
[LLVMdev] SoftenSetCCOpernads in LegalizeFloatTypes.cpp
Hi Sanjiv, I think a lot of the softening code assumes you are dealing with float (32 bits). So it's not just a matter of changing the libcall return type. > While generating a libcall from floating point comparison, it always > assumes that the return type of those libcalls is i32. > Why not allow Targets to provide the correct return type? > > EVT RetVT = MVT::i32;
2007 Dec 15
2
[LLVMdev] fix warning with newer g++ compilers
Ok, here is the patch again... I also included fixes for the bits that originally gave my mailer fits... Two votes for orange, so I went with orange... Doing diffs in .: --- ./lib/AsmParser/LLLexer.cpp.~1~ 2007-12-14 22:09:06.000000000 -0800 +++ ./lib/AsmParser/LLLexer.cpp 2007-12-15 13:02:47.000000000 -0800 @@ -54,7 +54,7 @@ static uint64_t HexIntToVal(const char * Result +=
2010 Jun 12
1
[LLVMdev] Memory leak?
Hi folk, I get the following stack trace and do have any clue how to fix the problem. 0 opt 0x087ecc99 1 opt 0x087ed265 2 0xb7f6a400 __kernel_sigreturn + 0 3 opt 0x086d4198 llvm::LeakDetector::addGarbageObject(llvm::Value const*) + 29 4 opt 0x0872945f llvm::Instruction::Instruction(llvm::Type const*, unsigned int,
2012 Dec 28
1
Using grImport to create a watermark
Hi… I want to use grImport to create a watermark on a plot() using the methods Paul Murrell describes here: http://cran.r-project.org/web/packages/grImport/vignettes/import.pdf (page 28). I can essentially reproduce this manually at the R prompt, and independently I can use grid.picture(…) successfully in a R script, but when I attempt to do do this in my script: • • •
2011 Aug 02
1
Compile Speex for Blackfin in VisualDsp
Hi, ? Is there a fix for this issue??? ---> http://permalink.gmane.org/gmane.comp.audio.compression.speex.devel/2959 ? I am seeing the same thing when I compile speex in visualdsp ? These are the errors I get from using the assembly version of vq_nbest: ? ..\..\..\..\algorithms\voice\speex\src\vq.c [Error ea5004] "C:\Users\coder\AppData\Local\Temp\acc22e8547f000\acc22e8547f001.s":482
2004 Oct 21
1
hi all
hi, i hv been burning nights reading howtos and manuals for iproute2 and iptables aiming at succesfully implementing a DMZ-NAT solution for our college (institute.) i am a student and never had past experience but hv used linux for quite some time now. so my first question is: do the functions of iptables and iproute2 overlap atall. i am preety confused regd this matter. 2nd: is it possible to
2017 Feb 25
2
Help understanding and lowering LLVM IDS conditional codes correctly
Note: Question is written after describing what I have coded. Hello LLVMDevs, I am trying to impliment floating point comparsion for an architecture which supports following type of floating point comparision if FPU is available: fcmp.un --> true if one of the operand is NaN fcmp.lt --> ordered less than, if any input NaN then return false fcmp.eq --> ordered equal, if any input NaN
2011 Jul 25
2
[LLVMdev] dragon egg adding extra characters to function names
Hello, I'm looking at compiling some pieces of the standard library with llvm but I'm running into problems with some functions being renamed by dragonegg. For example, when I compile the acos implementation with plain gcc I get: $ nm acos.o 0000000000000000 r .LC1 0000000000000048 r .LC10 0000000000000050 r .LC11 0000000000000058 r .LC12 0000000000000060 r .LC13 0000000000000068 r .LC14
2015 Feb 25
2
[LLVMdev] Question about shouldMergeGEPs in InstructionCombining
----- Original Message ----- > From: "Hal Finkel" <hfinkel at anl.gov> > To: "Francois Pichet" <pichet2000 at gmail.com> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, "chandlerc" <chandlerc at gmail.com> > Sent: Tuesday, February 24, 2015 11:27:43 PM > Subject: Re: [LLVMdev] Question about
2017 Dec 13
2
Is it possible to have two endpoints to the same IP address where one uses IP based authentication and the other requires asterisk to register to that system?
Currently using PJSIP. First, they want me to get this working with the existing PJSIP configuration, but then setup a second box using chan_sip performing similar work. For PJSIP... I currently have an endpoint configured to a system using IP based authentication. It is configured with a match setting in the endpoint section. All channels coming from that IP address go to this endpoint. They