similar to: Information Request

Hi! > According to the patch you send, the pass is not doing anything: > > +bool StackSegmenter::runOnMachineFunction(MachineFunction &MF) { > + return false; > +} > + It is, in the next patch. diff --git a/lib/CodeGen/StackSegmenter.cpp b/lib/CodeGen/StackSegmenter.cpp index 5ffb8f2..cc2ca87 100644 --- a/lib/CodeGen/StackSegmenter.cpp +++ b/lib/CodeGen/StackSegmenter.cpp

Inspection,Factory audit , purchasing agent in China This is Peter from Ningbo China.We have the team which is specialized in the quality inspection,factory audit,on line check,final shipment check and loading supervision etc.We have experienced quality engineers who had worked before in different third party inspection agencies like SGS,ITS etc and hence accumulated a lot of knowledges and

The code has changed a lot over the years. Looks like at some point of time the assumption was broken. calculateCallsInformation() may have eliminated the pseudo set up instructions already. // If call frames are not being included as part of the stack frame, and

On 10/10/11 19:19, Jakob Stoklund Olesen wrote: > On Oct 10, 2011, at 10:26 AM, Richard Osborne wrote: >> I'm investigating a bug associated with debug information that manifests >> itself in the XCore backend (PR11105). I'd like to understand what the >> expected behavior of eliminateFrameIndex() is when it is called on a >> dbg_value machine instruction. >

Thanks, I'll look into that. Still, the case where the function does not call anything remains---in such a situation there are no ADJCALLSTACK pseudos, so regardless of what that function you pointed at does, there won't be any target-independent information about the SP adjustment by the time the frame index elimination runs. Would it make sense to have ADJCALLSTACK pseudos every

The target description .td files are allowed to change the default allocation order on a register class by overriding the allocation_order_begin() and allocation_order_end() methods on TargetRegisterClass. Previously, this was used all the time to filter out stack and frame pointers and other reserved registers. I was able to remove most of these custom allocation orders in the tree because the

Hi All, I'm dealing with a problem where the spill/restore instructions inserted during scavenging span an adjustment of the SP/FP register. The result is that despite the base register (SP/FP) being changed between the spill and the restore, both store and load use the same immediate offset. I see code in the PEI (replaceFrameIndices) that is supposed to track the SP/FP adjustment:

Hi Chris, Your were totally right with your suggestion. I have implemented the code that : a) does not merge multiple TokenFactor nodes in the DAGCombiner::visitTokenFactor(), if the resulting TF node would contain more than 64 operands. b) produces a bunch of TokenFactor nodes with at most 64 operands, instead of one huge TokenFactor in the SelectionDAGLowering::getRoot(). If we have n

CallFrameSetupOpcode is a pseudo opcode like X86::ADJCALLSTACKDOWN64. That means when the code is expected to be called before the pseudo instructions are eliminated. I don't know why it's not the case for you. A quick look at PEI code indicates the pseudo's should not have been removed at the time when replaceFrameIndices are run. Evan On Sep 25, 2013, at 8:57 AM, Krzysztof

Hi Dan, Thanks for commenting on this topic. See my comments in-line. ----- Ursprüngliche Mail ---- > Von: Dan Gohman <gohman at apple.com> > An: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Gesendet: Mittwoch, den 30. April 2008, 21:38:26 Uhr > Betreff: Re: [LLVMdev] FoldingSetNodeID operations inefficiency > > > On Apr 28, 2008, at 6:21 AM, Roman

On Jun 27, 2008, at 3:11 AMPDT, Duncan Sands wrote: > FAIL: test/CodeGen/X86/vec_shuffle-10.ll > Failed with exit(1) at line 3 > while running: llvm-as < test/CodeGen/X86/vec_shuffle-10.ll | llc - > march=x86 -mattr=+sse2 | not grep {sub.*esp} > subl $16, %esp > subl $16, %esp > child process exited abnormally Is the code actually loading and storing

Hi Dale, yes it's just stack alignment. Unfortunately your patch doesn't make any difference. Thanks for thinking about this, Duncan. On Friday 27 June 2008 19:51:00 Dale Johannesen wrote: > On Jun 27, 2008, at 3:11 AMPDT, Duncan Sands wrote: > > FAIL: test/CodeGen/X86/vec_shuffle-10.ll > > Failed with exit(1) at line 3 > > while running: llvm-as <

On Jun 30, 2008, at 9:25 AMPDT, Duncan Sands wrote: > Hi Dale, yes it's just stack alignment. Unfortunately > your patch doesn't make any difference. > > Thanks for thinking about this, > > Duncan. OK, the test is not quite right then. This doesn't happen on Darwin so I'm afraid you'll have to debug it. Perhaps testing for

Hi Dale, > OK, the test is not quite right then. This doesn't happen on Darwin > so I'm > afraid you'll have to debug it. Perhaps testing for > (RegInfo->needsStackRealignment(Fn) && > FFI->getObjectIndexEnd()!=0) > ? yes, that works - thanks! Since I have no idea what this is doing, is it ok if I leave it to you to commit it?

On my (out-of-tree) target I have 16 128-bit registers. Unaligned load/store are illegal. (must 16-bytes aligned) 8 of those registers are defined as callee-saved and 8 caller-saved. The default stack size is 4 bytes. The target implements dynamic stack realign to make sure the stack will always be aligned correctly when necessary. Yet I am still getting unaligned load/store when running this

----- Original Message ----- > From: "Francois Pichet" <pichet2000 at gmail.com> > To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Monday, November 18, 2013 2:26:30 PM > Subject: [LLVMdev] Unaligned load/store for callee-saved 128-bit registers > > > > On my (out-of-tree) target I have 16 128-bit registers. >

Mehdi, I am perusing the 3.8 trunk sources, and don’t find evidence where I would expect it for LLVM “downgrading” a function’s calling convention. PrologEpilogEmitter() { “CodeGen/” ... TFI->determineCalleeSaves() { “Target/XYZ/” TargetFrameLowering::determineCalleeSaves() { “CodeGen/” Return <<< some object derived

Consider this example: --- ex.ll --- declare void @bar() ; Function Attrs: nounwind optsize define void @main() { entry: %hin = alloca [256 x i32], align 4 %xin = alloca [256 x i32], align 4 call void @bar() ret void } ------------- Freshly built llc: llc -O2 -march=x86 < ex.ll -print-before-all # *** IR Dump Before Prologue/Epilogue Insertion & Frame Finalization ***: #

I have a question about register scavenger. I am considering using register scavenger for MIPS to free up register AT which is currently reserved to load large immediates. All targets which currently use register scavenger to search for a scratch register (ARM, CellSPU, PowerPC and XCore) override function processFunctionBeforeCalleeSavedScan and call RegisterScavenger::setScavengingFrameIndex

Hi, My problem does not happen all the time, nor with all files I save to csv format. I can send my test file (format rda or csv) to whoever would like to replicate (and hopefully explain) my problem. In short, I have a dataset with mostly numerical variables. One of my variable is called pfi2 and is definitely numerical, as shown by this: > summary(test$pfi2) Min. 1st Qu. Median