similar to: [PATCH] gm107/ir: fix texture argument order

Displaying 20 results from an estimated 400 matches similar to: "[PATCH] gm107/ir: fix texture argument order"

2014 Mar 20
0
[PATCH] nvc0/ir: move sample id to second source arg to fix sampler2DMS
The nvc0 texfetch instruction expects the sample id to be in the second source (usually used for the offset) rather than as part of the texture coordinate. This fixes all the sampler2DMS/Array tests on nvc0. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.1" <mesa-stable at lists.freedesktop.org> --- Tested on nvc1 with a full piglit run, no regressions,
2014 Aug 08
2
[PATCH 1/3] nvc0/ir: add base tex offset for fermi indirect tex case
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index f010767..4a9e48f 100644 ---
2014 Apr 04
2
[PATCH 1/2] nvc0: add support for texture gather
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Tested on NVE6. Very strange that it seems to use 8 bits for offsets, vs 4 bits used by texelFetch. But this passes the piglit tests. Will test on a NVCX before checking in, in case it's different there. (Although that'd be surprising, given the similarities between the 2 ISAs.)
2014 Jul 05
1
[PATCH 1/2] nvc0/ir: use manual TXD when offsets are involved
Something about how we're implementing offsets for TXD is wrong, just flip to the generic quadop-based implementation in that case. This is the minimal fix appropriate for backporting. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: <mesa-stable at lists.freedesktop.org> --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 3 ++- 1 file changed, 2
2014 Feb 28
0
[PATCH] nv50: enable texture query lod
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Note: this applies on top of airlied's r600g-texture-gather branch. Appears to pass all 4 piglit tests. The conversion from what the instruction outputs is the same as what the blob does. src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 + .../drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 4 ++++
2015 Jan 04
0
[PATCH] nv50/ir: fix texture offsets in release builds
assert's get compiled out in release builds, so they can't be relied upon to perform logic. Reported-by: Pierre Moreau <pierre.morrow at free.fr> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.2 10.3 10.4" <mesa-stable at lists.freedesktop.org> --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp | 3 ++-
2014 Feb 19
0
[PATCH] nv50: enable cube map array texture support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- All the arb_texture_cube_map_array piglits pass except the sampler-cube-shadow one. However, nva0+ appear to all fail at the non-array version of that test, sampler-cube-shadow, so I think it's very likely to be related. Probably some sampler setup bits changed. src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp | 5
2017 Dec 20
0
[PATCH] gm107/ir: use lane 0 for manual textureGrad handling
On Tue, Dec 19, 2017 at 11:41 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > This is parallel to the pre-SM50 change which does this. Adjusts the > shuffles / quadops to make the values correct relative to lane 0, and > then splat the results to all lanes for the final move into the target > register. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> >
2019 Oct 14
1
[PATCH] gm107/ir: fix loading z offset for layered 3d image bindings
Unfortuantely we don't know if a particular load is a real 2d image (as would be a cube face or 2d array element), or a layer of a 3d image. Since we pass in the TIC reference, the instruction's type has to match what's in the TIC (experimentally). In order to properly support bindless images, this also can't be done by looking at the current bindings and generating appropriate
2017 Dec 20
2
[PATCH] gm107/ir: use lane 0 for manual textureGrad handling
This is parallel to the pre-SM50 change which does this. Adjusts the shuffles / quadops to make the values correct relative to lane 0, and then splat the results to all lanes for the final move into the target register. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Entirely untested beyond compilation. Should check bin/tex-miplevel-selection textureGrad Cube
2014 May 13
1
[PATCH 1/2] nv50/ir: make sure that texprep/texquerylod's args get coalesced
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.2" <mesa-stable at lists.freedesktop.org> --- Not 100% sure of the significance of this code, but this seems like the correct thing to do... will definitely run it through a full piglit run before pushing out. src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git
2014 Feb 20
0
[PATCH] nv50: enable txg where supported
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- This applies on top of Dave Airlie's r600g-texture-gather branch. Ran piglit with -t gather, passed all 1057 tests. Can't say I fully understand what all the arguments to handleTEX in the Coverter are but... seems to work. Will probably require some care for nvc0 support which should have SM5 caps.
2014 Jul 05
0
[PATCH] nvc0: do quadops on the right texture coordinates for TXD
handleTEX moves the layer as the first argument. This makes sure that the quadops deal with the texture coordinates. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: <mesa-stable at lists.freedesktop.org> --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git
2013 Dec 08
0
[PATCH] nv50: TXF already has integer arguments, don't try to convert from f32
Fixes the texelFetch piglit tests. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Verified a few things, but it's hard to check this fully. They array-texture piglit test fails if the conversion isn't done at all, and texelFetch starts passing if the conversion is removed. Dunno if this is the sort of thing worth sticking a stable tag on, so leaving it out. Feel free to
2014 Jul 05
1
[PATCH 1/2] nv50/ir: retrieve shadow compare from first arg
This can only happen with texture(samplerCubeShadow, bias), where the compare will be in the first argument. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: <mesa-stable at lists.freedesktop.org> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git
2015 Nov 26
0
NV50 compute support questions
Well, if you remove that assert locally, all compute tests in src/gallium/tests/trivial/compute.c pass on GK106, except the atomic ones. I'm working on the fermi case btw. On 11/25/2015 03:43 PM, Hans de Goede wrote: > Hi, > > On 20-11-15 17:07, Samuel Pitoiset wrote: >> >> >> On 11/20/2015 11:36 AM, Hans de Goede wrote: >>> Hi Samual, et al, >>
2015 Nov 26
0
NV50 compute support questions
On 11/26/2015 01:21 PM, Hans de Goede wrote: > Hi, > > On 26-11-15 09:42, Samuel Pitoiset wrote: >> Well, if you remove that assert locally, all compute tests in >> src/gallium/tests/trivial/compute.c pass on GK106, except the atomic >> ones. > > Do you mean the: > > Assertion `pres->target != PIPE_BUFFER' failed. > > or the: > >
2015 Nov 25
0
NV50 compute support questions
On 11/25/2015 03:43 PM, Hans de Goede wrote: > Hi, > > On 20-11-15 17:07, Samuel Pitoiset wrote: >> >> >> On 11/20/2015 11:36 AM, Hans de Goede wrote: >>> Hi Samual, et al, >> >> Hi Hans, >> >>> >>> In >>>
2017 Aug 11
2
[PATCH] nv50/ir: Initialize all members of GCRA (trivial)
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> --- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp index 9d70ec3c9c..e4f38c8e46 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++
2015 Nov 26
2
NV50 compute support questions
Hi, On 26-11-15 09:42, Samuel Pitoiset wrote: > Well, if you remove that assert locally, all compute tests in src/gallium/tests/trivial/compute.c pass on GK106, except the atomic ones. Do you mean the: Assertion `pres->target != PIPE_BUFFER' failed. or the: Assertion `tex->defExists(0) && tex->srcExists(0)' failed. assert? Or is the first one not present for