similar to: [PATCH] drm: platform: update moved Tegra header

On 02:29:32PM Jan 06, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Tue, Jan 06, 2015 at 08:03:03PM +0800, Vince Hsu wrote: > > On 01/06/2015 07:15 PM, Thierry Reding wrote: > > >> Old Signed by an unknown key > > > > > >On Tue, Jan 06, 2015 at 10:11:41AM +0800, Vince Hsu wrote: > > >>On 01/05/2015 11:09 PM, Thierry Reding

On 01/06/2015 07:15 PM, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Tue, Jan 06, 2015 at 10:11:41AM +0800, Vince Hsu wrote: >> On 01/05/2015 11:09 PM, Thierry Reding wrote: >>>> Old Signed by an unknown key >>> On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu wrote: >>>> On 12/24/2014 09:16 PM, Lucas Stach wrote:

On Tue, Jan 06, 2015 at 08:03:03PM +0800, Vince Hsu wrote: > On 01/06/2015 07:15 PM, Thierry Reding wrote: > >* PGP Signed by an unknown key > > > >On Tue, Jan 06, 2015 at 10:11:41AM +0800, Vince Hsu wrote: > >>On 01/05/2015 11:09 PM, Thierry Reding wrote: > >>>>Old Signed by an unknown key > >>>On Thu, Dec 25, 2014 at 10:28:08AM +0800,

On 01/05/2015 11:09 PM, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu wrote: >> On 12/24/2014 09:16 PM, Lucas Stach wrote: >>> Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: >>>> The Tegra124 and later Tegra SoCs have a sepatate rail gating register >>>> to enable/disable

On Tue, Jan 06, 2015 at 10:11:41AM +0800, Vince Hsu wrote: > > On 01/05/2015 11:09 PM, Thierry Reding wrote: > >* PGP Signed by an unknown key > > > >On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu wrote: > >>On 12/24/2014 09:16 PM, Lucas Stach wrote: > >>>Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > >>>>The Tegra124

Add a platform driver for Nouveau devices declared using the device tree or platform data. This driver currently supports GK20A on Tegra platforms and is only compiled for these platforms if Nouveau is enabled. Nouveau will probe the chip type itself using the BOOT0 register, so all this driver really needs to do is to make sure the module is powered and its clocks active before calling

op 26-06-14 07:33, Alexandre Courbot schreef: > Add a platform driver for Nouveau devices declared using the device tree > or platform data. This driver currently supports GK20A on Tegra > platforms and is only compiled for these platforms if Nouveau is > enabled. > > Nouveau will probe the chip type itself using the BOOT0 register, so all > this driver really needs to do is

GM20B requires an extra clock compared to GK20A. Add that information into the platform data and acquire and enable this clock if necessary. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- Hi Ben, The DT bindings for this have been approved but not merged yet. This means that for 4.6 GM20B will fail to probe unless the DT is patched - but this is better than the current

On Tue, Jan 06, 2015 at 03:18:22PM +0100, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Tue, Dec 23, 2014 at 06:39:55PM +0800, Vince Hsu wrote: > > The flush operation of memory clients is needed for various IP blocks in > > the Tegra SoCs to perform a clean reset. > > > > Signed-off-by: Vince Hsu <vinceh at nvidia.com> > > --- >

On Wed, Jan 07, 2015 at 06:49:27PM +0800, Vince Hsu wrote: > > On 01/07/2015 06:19 PM, Peter De Schrijver wrote: > >On Mon, Jan 05, 2015 at 04:09:33PM +0100, Thierry Reding wrote: > >>* PGP Signed by an unknown key > >> > >>On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu wrote: > >>>On 12/24/2014 09:16 PM, Lucas Stach wrote: >

On Wed, Jan 07, 2015 at 06:49:27PM +0800, Vince Hsu wrote: > > On 01/07/2015 06:19 PM, Peter De Schrijver wrote: > >On Mon, Jan 05, 2015 at 04:09:33PM +0100, Thierry Reding wrote: > >>* PGP Signed by an unknown key > >> > >>On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu wrote: > >>>On 12/24/2014 09:16 PM, Lucas Stach wrote: >

On Wed, Jan 07, 2015 at 10:19:52PM +0800, Vince Hsu wrote: > On 04:12:54PM Jan 07, Peter De Schrijver wrote: > > On Wed, Jan 07, 2015 at 06:49:27PM +0800, Vince Hsu wrote: > > > > > > On 01/07/2015 06:19 PM, Peter De Schrijver wrote: > > > >On Mon, Jan 05, 2015 at 04:09:33PM +0100, Thierry Reding wrote: > > > >>* PGP Signed by an unknown key

On Tue, Dec 23, 2014 at 06:39:55PM +0800, Vince Hsu wrote: > The flush operation of memory clients is needed for various IP blocks in > the Tegra SoCs to perform a clean reset. > > Signed-off-by: Vince Hsu <vinceh at nvidia.com> > --- > drivers/memory/tegra/mc.c | 21 +++++++++++++++++++++ > include/soc/tegra/mc.h | 23 ++++++++++++++++++++++- > 2 files changed,

This patch adds some missing pieces of the rail gaing/ungating sequence that can improve the stability in theory. Signed-off-by: Vince Hsu <vinceh at nvidia.com> --- drm/nouveau_platform.c | 42 ++++++++++++++++++++++++++++++++++++++++++ drm/nouveau_platform.h | 3 +++ 2 files changed, 45 insertions(+) diff --git a/drm/nouveau_platform.c b/drm/nouveau_platform.c index

The Tegra124 and later Tegra SoCs have a sepatate rail gating register to enable/disable the clamp. The original function tegra_powergate_remove_clamping() is not sufficient for the enable function. So add a new function which is dedicated to the GPU rail gating. Also don't refer to the powergate ID since the GPU ID makes no sense here. Signed-off-by: Vince Hsu <vinceh at nvidia.com>

On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu wrote: > On 12/24/2014 09:16 PM, Lucas Stach wrote: > >Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > >>The Tegra124 and later Tegra SoCs have a sepatate rail gating register > >>to enable/disable the clamp. The original function > >>tegra_powergate_remove_clamping() is not sufficient for the

On 12/24/2014 09:23 PM, Lucas Stach wrote: > Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: >> This patch adds some missing pieces of the rail gaing/ungating sequence that >> can improve the stability in theory. >> >> Signed-off-by: Vince Hsu <vinceh at nvidia.com> >> --- >> drm/nouveau_platform.c | 42

Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > This patch adds some missing pieces of the rail gaing/ungating sequence that > can improve the stability in theory. > > Signed-off-by: Vince Hsu <vinceh at nvidia.com> > --- > drm/nouveau_platform.c | 42 ++++++++++++++++++++++++++++++++++++++++++ > drm/nouveau_platform.h | 3 +++ > 2 files changed, 45

On Mon, Jan 05, 2015 at 04:09:33PM +0100, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Thu, Dec 25, 2014 at 10:28:08AM +0800, Vince Hsu wrote: > > On 12/24/2014 09:16 PM, Lucas Stach wrote: > > >Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: > > >>The Tegra124 and later Tegra SoCs have a sepatate rail gating register > >

On 12/24/2014 09:16 PM, Lucas Stach wrote: > Am Dienstag, den 23.12.2014, 18:39 +0800 schrieb Vince Hsu: >> The Tegra124 and later Tegra SoCs have a sepatate rail gating register >> to enable/disable the clamp. The original function >> tegra_powergate_remove_clamping() is not sufficient for the enable >> function. So add a new function which is dedicated to the GPU rail