similar to: [PATCH] drm/nouveau/fb: Prevent inlining of ramfuc_reg

Patch 1 fixes nva3 bailing due to not finding the right ramcfg Patch 2 is a resend rebased on 3.17.0-rc4 for setting the vblank period Patch 3-5 handle writes to per-partition registers, for which NVA3 does not have special broadcast regs available. Patch 6 removes local structs from NVA3 reclocking in favour of the already existing "ram->base." variables, like in NVE0 As always,

Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/core/include/subdev/pwr.h | 2 + drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h | 16 ++ drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c | 318 +++++++++++++++++++-- .../gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc | 111 +++++++ drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h | 5 +

Following a series of patches that implement memory reclocking for NVA3/5/8 with DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics cards, but I expect reclocking now to work on many more. Testers can pick up these patches and test it by enabling pstate (nouveau.pstate=1). They should then be able to change clocks by writing to /sys/class/drm/card0/device/pstate. Correct

No, no, these will not implement Fermi reclocking. This set of patches contains some of the preparatory work that I deem stable enough to move upstream. Notable changes - Training pattern upload routines from GK104+ now shared with GT215+ - Timing calculation for Fermi - GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that pesky GT 240. - A routine to translate a VBIOS init

Two patches went missing as a result of PEBCAK. No v2 marks as nothing changed really. Just resending for easier enforcement of patch order in other people's trees. Sorry for the noise. Original message: No, no, these will not implement Fermi reclocking. This set of patches contains some of the preparatory work that I deem stable enough to move upstream. Notable changes - Training pattern

Signed-off by: Rosen Penev <rosenp at gmail.com> --- drm/nouveau/nvkm/subdev/fb/ramgf100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drm/nouveau/nvkm/subdev/fb/ramgf100.c index 4a9bd4f1..feb8820c 100644 --- a/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -717,7 +717,7 @@

This is fixed in a different nouveau branch. from Ben Skeggs last I remember. On Fri, Dec 29, 2017 at 1:37 PM, Pierre Moreau <pierre.morrow at free.fr> wrote: > The typo is still present in master. > Not sure whether it will help you Ben, regarding Fermi reclocking, but it > shouldn’t harm in reducing possible errors. :-) > > Regards, > Pierre > > On 2017-07-27 —

In bulletpoints: - Add some support for G94 and G96 reclocking. Has been tested on literally two cards, which is hardly adequate as "full coverage". On the other hand, the changes were small enough to make me confident this might work for others as well. - Fix NV50 wait for VBLANK when no monitor is plugged in. - Voltage related inprovements for GT21x. - Slightly improve Keplers

Todo: - Determine source of R[10f298] & 0x11 Signed-off-by: Roy Spliet <nouveau at spliet.org> --- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 115 ++++++++++++++-------- 1 file changed, 76 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index fffd01a..6ebdc4c 100644 ---

Merges in skeggsb's: "fb/ram/gf10x: timing_10_0e_30" Todo: - find l3, rq - triple-check Signed-off-by: Roy Spliet <nouveau at spliet.org> --- .../drm/nouveau/include/nvkm/subdev/bios/ramcfg.h | 12 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c | 22 ++++++++-- drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c | 2 +

Needs to be done after wait-for-VBLANK, and NVA3 requires register writes in between. Rather than hard-coding register writes, just split out fb_disable and fb_enable. Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/core/include/subdev/pwr.h | 2 ++ drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h | 14 ++++++++++++++

Signed-off-by: Roy Spliet <nouveau at spliet.org> --- drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h | 2 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h | 8 +++ drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c | 66 +++++++++++++++++++++++ 3 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h

The typo is still present in master. Not sure whether it will help you Ben, regarding Fermi reclocking, but it shouldn’t harm in reducing possible errors. :-) Regards, Pierre On 2017-07-27 — 18:20, Rosen Penev wrote: > Signed-off by: Rosen Penev <rosenp at gmail.com> > --- > drm/nouveau/nvkm/subdev/fb/ramgf100.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >

Patch 1 and 2 implement wait-for-vblank, required to remove flicker when reclocking memory Patch 3 and 4 allow me to do things between waiting for VBLANK and disabling FB, like pause PFIFO and wait for the engines to idle. This minimises the time PFIFO is paused, thus maximises performance. The rest of the patches speak for themselves. As the actual memory reclocking script is still somewhat prone

Hello, Attached a small patch that correctly identifies the DLLoff bit for >=GF100. Marked RFC because I haven't seen any GDDR5 samples that *enable* the DLL. I'd like to verify whether the DLL should be reset when enabled. Could increase likelihood of succesfull reclock. Ben: could you do some experiments with this bit to see if GDDR5 needs some DLL reset logic? Thanks, and happy

Signed-off-by: Roy Spliet <nouveau at spliet.org> Tested-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c | 128 +++++++++++++++++----- 2 files changed, 99 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h

Hi, As part of aiming at upstreaming our code, I suppose we have to discuss the DRM situation a little. In order to aim for merging, I think we'd better be working on a linux kernel tree layout. And considering we're technically the only ones still working in drm.git, it doesn't really make sense to keep doing that for the sake of sharing code with other drivers. As we discussed on

https://bugs.freedesktop.org/show_bug.cgi?id=107874 Bug ID: 107874 Summary: Incorrect SPDX-License-Identifier on various nouveau drm kernel source files? Product: xorg Version: unspecified Hardware: Other OS: NetBSD Status: NEW Severity: normal Priority: medium

This isn't needed any longer (DRI1 is gone) so let's remove this as well. Signed-off-by: Stéphane Marchesin <marcheu at chromium.org> --- src/nv_include.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/nv_include.h b/src/nv_include.h index de55570..eee8c5d 100644 --- a/src/nv_include.h +++ b/src/nv_include.h @@ -69,6 +69,5 @@ #include "nv_type.h" #include

Hi, I'm working with Oliver McFadden to create a rules-ng database for the Radeon R300 (and beyond..) I've taken some of the work that he had done, and have been slowly adding more Radeon registers. I also created a new 'test-r300' app based on the one included in the static-db to test the decode of radeon registers. I would like this to be under version control, and the