similar to: Proper gl_SampleMask output

Hi Ilia. I'll take a look and see what I can find out. Thanks, - Andy On Wed, Apr 23, 2014 at 05:03:17PM -0700, Ilia Mirkin wrote: > On Wed, Apr 23, 2014 at 6:22 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > > Hello, > > > > I've been trying to add ARB_sample_shading support to nouveau, and am > > being defeated by the gl_SampleMask tests.

On Wed, Apr 23, 2014 at 6:22 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > Hello, > > I've been trying to add ARB_sample_shading support to nouveau, and am > being defeated by the gl_SampleMask tests. Everything else works fine. > (And naturally the tests pass with the proprietary driver.) I'm trying > to do this for both GT21x, as well as GF100+. > > In

Great, thanks! I've looked at a bunch more shaders (unrelated to this) in the meanwhile, and I'm pretty sure the extra FMA business is totally unrelated to the issue at hand. It appears that the NVIDIA driver generates shaders that are capable of transforming the output coordinates arbitrarily, whereas mesa-generated shaders (and by extension, nouveau's) only put in the specific needs

Some shaders appear to extract bits using shift/and combos. Detect (some) of those and convert to EXTBF instead. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 66 +++++++++++++++------- 1 file changed, 46 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Pretty sure there's nothing wrong with it, but it looks odd in the code. src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 ++ src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 7 +++++-- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 ++ 3 files changed, 9 insertions(+), 2 deletions(-)

v4: Updated the wait dependancy bars based on tex component masks. This patch adds proper delays to maxwell exa shaders. Tested with rendercheck -f a8r8g8b8. I am still wondering whether the rd's are required. We could still wait on the write bars instead. eg. see "sched (st 0xf wr 0x1 wt 0x2) (st 0xf wr 0x1 wt 0x2) (st 0xf)" in exacmnv110.fp Trello:

Removed explicit depar instructions as they're not used by the blob anymore. Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com> --- src/shader/exac8nv110.fp | 5 ++--- src/shader/exac8nv110.fpc | 10 ++++------ src/shader/exacanv110.fp | 5 ++--- src/shader/exacanv110.fpc | 10 ++++------ src/shader/exacmnv110.fp | 5 ++--- src/shader/exacmnv110.fpc | 10 ++++------

This patch adds proper delays to maxwell exa shaders. rendercheck tests seem consistent with/without this patch. I haven't extensively tested them though. Trello: https://trello.com/c/6LPB2EIS/174-update-maxwell-shaders-with-proper-delays Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com> --- src/shader/exac8nv110.fp | 10 +++++----- src/shader/exac8nv110.fpc | 18

v2: Add missing delays This patch adds proper delays to maxwell exa shaders. rendercheck tests seem consistent with/without this patch. I haven't extensively tested them though. Trello: https://trello.com/c/6LPB2EIS/174-update-maxwell-shaders-with-proper-delays Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com> --- src/shader/exac8nv110.fp | 10 +++++-----

On Tue, Jun 6, 2017 at 7:15 AM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > Nice work! > > See my comments below, and double-check if some of them can be applied to > the shaders I didn't review yet. > > I recommend you to test your work because if one sched code is wrong, you > are likely going to kill your card and reboot your box. :-) > > >

rendercheck -f a8r8g8b8 passes as much as on a GK208, and xv appears to work. Very lightly tested. Instead of sticking coordinates into pushbufs, the vertex shader is modified to read them from a constbuf, indexed by vertex id. This approach could be used for all nvc0 generations, but I didn't want to rock the boat. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Note: this

I believe I've addressed all the feedback from the first time around, and also made fixes necessary for GM20x based on testing results. I believe now it should actually work for all GM10x and GM20x. Further, GP10x should be very easy to add, but without someone to actually test I didn't want to claim support for it. Ilia Mirkin (7): exa: add GM10x acceleration support hwdefs: update

Hi, On Wed, Jun 28, 2017 at 12:53 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > BTW, you can drop those explicit "depbar" ops. I think they're only > needed when you're doing something weird with barriers. Blob doesn't > use them (anymore) > Gotcha. Should I remove them in the same patch or a different one? It seems like the depbar removal is

On Thu, Jun 8, 2017 at 5:01 AM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > > > On 06/07/2017 06:58 PM, Aaryaman Vasishta wrote: > >> >> >> On Tue, Jun 6, 2017 at 7:15 AM, Samuel Pitoiset < >> samuel.pitoiset at gmail.com <mailto:samuel.pitoiset at gmail.com>> wrote: >> >> Nice work! >> >> See my

I'm a mathematician and programmer working on experimental surround sound techniques. Some of the ideas I'm working on require dozens of channels. These channels are often highly correlated and are very well suited to compression. I'm new to Vorbis. Does it attempt to address such issues? Thanks, --Richard --- >8 ---- List archives: http://www.xiph.org/archives/ Ogg project

# uname -a Linux ns2 2.6.18-4-sparc64 #1 Mon Mar 26 11:16:07 UTC 2007 sparc64 GNU/Linux # dovecot -n # 1.0.1: /usr/local/etc/dovecot.conf Segmentation fault uhu? ciao Luca

Unfortunately there's no sure-fire way to distinguish a sched "op" from regular ones. They happen purely based on position. So for disassembly, use the byte position in the file to determine whether the current op should be decoded as sched or as regular. For assembly, we go back to using a shared table. Ideally we would pick out which one to use based on the position in the

Corresponds with GT215. Don't rely on the lock test logic being unconditionally enabled, and disable test logic when done (presumably to save power). Warn when locking fails. Signed-off-by: Roy Spliet <nouveau at spliet.org> --- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 15 ++++++++++++--- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 15 ++++++++++++--- 2 files changed, 24

Corresponds with GT215. Don't rely on the lock test logic being unconditionally enabled, and disable test logic when done (presumably to save power). v2: Remove warning, nvkm_msec already warns on time-out Signed-off-by: Roy Spliet <nouveau at spliet.org> --- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 8 +++++++- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 8 +++++++- 2

If it's anything like the rooms I saw last year...some rooms have "wardrobes" meaning that you have a unit with a shelf, a "closet" cabinet type thing, and about 5 drawers. If you have lots of clothes, bring extra storage containers because thos drawers can't really hold much. Or don't bring so many clothes:) I think some of the two room doubles have huge-ass floor