similar to: [PATCH] drm/nouveau/vdec: copy nvc0 bsp/vp/ppp to nv98

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to do the rest of

Add a GR device for GK20A based on NVE4, with the correct classes definitions (GK20A's 3D class is 0xa297). Most of the NVE4 code can be used on GK20A, so make relevant bits of NVE4 available to other chips as well. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/Makefile | 1 + .../gpu/drm/nouveau/core/engine/graph/ctxnve4.c

On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot <acourbot at nvidia.com> wrote: > Add a GR device for GK20A based on NVE4, with the correct classes > definitions (GK20A's 3D class is 0xa297). > > Most of the NVE4 code can be used on GK20A, so make relevant bits of > NVE4 available to other chips as well. This will need a bit of a rebase on top of the tree I mentioned

On Mon, Jun 3, 2013 at 5:02 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > These chipsets include the VP2 engine which is composed of a bitstream > processor (BSP) that decodes H.264 and a video processor (VP) which can > do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are > driven by separate xtensa chips embedded in the hardware. This patch > provides the

From: Ben Skeggs <bskeggs at redhat.com> The kernel previously exposed incorrect classes for some of the chipsets that this code supports. It no longer does, but the older object ioctls have compatibility to avoid breaking userspace. This needs to be fixed before switching over to the newer interfaces. Rather than hardcoding chipset->class like the rest of the driver does, this makes

On 26 November 2015 at 07:15, Ben Skeggs <skeggsb at gmail.com> wrote: > +static const struct nouveau_mclass > +nv98_decoder_msvld[] = { > + { 0x88b1, -1 }, > + { 0x86b1, -1 }, > + { 0x85b1, -1 }, > + {} > +}; > + > +static const struct nouveau_mclass > +nv98_decoder_mspdec[] = { > + { 0x88b2, -1 }, > + { 0x85b2, -1 }, > + {} > +};

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to do the rest of

704a6c008b7942bb7f30bb43d2a6bcad7f543662 broke pci msi rearm for g92 GPUs. g92 needs the nv46_pci_msi_rearm, where g94+ gpus used nv40_pci_msi_rearm. Reported-by: Andrew Randrianasulu <randrianasulu at gmail.com> Signed-off-by: Karol Herbst <karolherbst at gmail.com> --- drm/nouveau/include/nvkm/subdev/pci.h | 1 + drm/nouveau/nvkm/engine/device/base.c | 20 +++++++-------

Fixes failure to compile with recent envyas as a result of the 'movw' alias being removed for v5. A bit of history: v3 only has a 16-bit sign-extended immediate mov op. In order to set the high bits, there's a separate 'sethi' op. envyas validates that the value passed to mov(imm) is between -0x8000 and 0x7fff. In order to simplify macros that load both the low and high word,

on gk208+ we can simply mov 32bits, so we should have a single mov there Signed-off-by: Karol Herbst <nouveau at karolherbst.de> --- drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h | 1598 +++++++++++------------ drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h | 1494 +++++++++++----------- drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h | 1424 ++++++++++-----------

On 11/11/2015 06:07 PM, Alexandre Courbot wrote: > Commit 69c4938249fb ("drm/nouveau/instmem/gk20a: use direct CPU access") > tried to be smart while using the DMA-API by managing the CPU mappings of > buffers allocated with the DMA-API by itself. In doing so, it relied > on dma_to_phys() which is an architecture-private function not > available everywhere. This broke the

Hi everyone, Here is the second batch of patches to add GK20A support to Nouveau. This time we are adding the actual chip support, and this series brings the driver to a point where a slightly-tweaked Mesa successfully runs shaders and renders triangles on GBM! Many thanks to Thierry Reding and the people on the #nouveau IRC channel for their help without which we would not have reached this

Hi Martin, I'm not very familiar with the function naming scheme but shouldn't nouveau_fuse_rd32 use the same prefix as xxxx_fuse_ctor instead of nouveau? Christian Le 24/08/2014 23:15, Martin Peres a ?crit : > We will use this subdev to disable temperature reading on cards that did not > get a sensor calibration in the factory. > > Signed-off-by: Martin Peres

Abuse of function pointer was noticed by sparse. Signed-off-by: Marcin Slusarz <marcin.slusarz at gmail.com> --- drivers/gpu/drm/nouveau/nv50_evo.c | 18 ++++++++++++------ 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c index 0f53416..0483cbd 100644 --- a/drivers/gpu/drm/nouveau/nv50_evo.c +++

Latest patches for GK20A, taking comments received for v3 into account. Changes since v3: - use only pfn_to_page() and page_to_pfn() in GK20A's FB. These functions are present on every arch and the physical address to page frame number conversion is also consistently a shift of PAGE_SHIFT. This part will probably be replaced by something nicer in the future anyway. - fixed a warning on

Hi everyone, Way overdue v2 of the final patches that enable basic GK20A support. Hopefully all the issues raised with v1 have been addressed. Changes since v1: - Use gk20a clock driver by Ben instead of twiddling nv04's - Name new classes after gk20a instead of nvea - Addressed comments about BAR initialization code factorization - Removed non-essential code which only purpose was to avoid

Changes since v2: - Enabled software class - Removed unneeded changes to nouveau_accel_init() - Replaced use of architecture-private pfn_to_dma() and dma_to_pfn() with the portable page_to_phys()/phys_to_page() - Fixed incorrect comment/commit log talking about bytes instead of words Hope this looks good! Once this gets merged the next set will be to use this driver on Jetson and Venice2

Commit 69c4938249fb ("drm/nouveau/instmem/gk20a: use direct CPU access") tried to be smart while using the DMA-API by managing the CPU mappings of buffers allocated with the DMA-API by itself. In doing so, it relied on dma_to_phys() which is an architecture-private function not available everywhere. This broke the build on several architectures. Since there is no reliable and portable

Signed-off-by: Karol Herbst <nouveau at karolherbst.de> --- drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h | 882 +++++++++++++-------------- drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc | 2 +- 2 files changed, 442 insertions(+), 442 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h b/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h index 8a2b628..11179c1 100644 ---

>From recent additional locking in nouveau, it looks like we see recursive lock acquisition in 3.8-rc6: nouveau [ DEVICE][0000:01:00.0] BOOT0 : 0x0e7150a2 nouveau [ DEVICE][0000:01:00.0] Chipset: GK107 (NVE7) nouveau [ DEVICE][0000:01:00.0] Family : NVE0 nouveau [ VBIOS][0000:01:00.0] checking PRAMIN for image... nouveau [ VBIOS][0000:01:00.0] ... appears to be valid nouveau [