similar to: [PATCH] nv50: H.264/MPEG2 decoding support via VP2, available on NV84-NV96, NVA0

Adds H.264 and MPEG2 codec support via VP2, using firmware from the blob. Acceleration is supported at the bitstream level for H.264 and IDCT level for MPEG2. Known issues: - H.264 interlaced doesn't render properly - H.264 shows very occasional artifacts on a small fraction of videos - MPEG2 + VDPAU shows frequent but small artifacts, which aren't there when using XvMC on the same

On Sat, Jun 29, 2013 at 2:07 PM, Emil Velikov <emil.l.velikov at gmail.com> wrote: > Hi Ilia, > > On 27/06/13 12:26, Ilia Mirkin wrote: >> Adds H.264 and MPEG2 codec support via VP2, using firmware from the >> blob. Acceleration is supported at the bitstream level for H.264 and >> IDCT level for MPEG2. >> >> Known issues: >> - H.264 interlaced

Hi Ilia, On 27/06/13 12:26, Ilia Mirkin wrote: > Adds H.264 and MPEG2 codec support via VP2, using firmware from the > blob. Acceleration is supported at the bitstream level for H.264 and > IDCT level for MPEG2. > > Known issues: > - H.264 interlaced doesn't render properly > - H.264 shows very occasional artifacts on a small fraction of videos > - MPEG2 + VDPAU

On 29/06/13 21:21, Ilia Mirkin wrote: > On Sat, Jun 29, 2013 at 2:07 PM, Emil Velikov <emil.l.velikov at gmail.com> wrote: >> Hi Ilia, >> >> On 27/06/13 12:26, Ilia Mirkin wrote: >>> Adds H.264 and MPEG2 codec support via VP2, using firmware from the >>> blob. Acceleration is supported at the bitstream level for H.264 and >>> IDCT level for

As it turns out, with the proprietary firmware, the VP3 and VP4 interfaces are identical. Furthermore, this is all already implemented for nvc0. So these patches (a) move the easily sharable bits of the nvc0 implementation into the nouveau directory, and then (b) implement the other parts in nv50. The non-shared parts are still largely copies, but there are some differences, not the least of which

The mt address is about to be used more, make sure it's set appropriately. Reported-by: Emil Velikov <emil.l.velikov at gmail.com> Tested-by: Emil Velikov <emil.l.velikov at gmail.com> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.2 10.3" <mesa-stable at lists.freedesktop.org> --- src/gallium/drivers/nouveau/nv50/nv84_video.c | 2 ++ 1 file

Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- src/gallium/drivers/nouveau/nouveau_fence.c | 76 ++++++++++++------------- src/gallium/drivers/nouveau/nouveau_fence.h | 22 +++++-- src/gallium/drivers/nouveau/nouveau_screen.c | 9 +++ src/gallium/drivers/nouveau/nouveau_screen.h | 14 ++--- src/gallium/drivers/nouveau/nv30/nv30_context.c | 4 +-

Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- src/gallium/drivers/nouveau/nouveau_fence.c | 76 ++++++++++++------------- src/gallium/drivers/nouveau/nouveau_fence.h | 22 +++++-- src/gallium/drivers/nouveau/nouveau_screen.c | 9 +++ src/gallium/drivers/nouveau/nouveau_screen.h | 14 ++--- src/gallium/drivers/nouveau/nv30/nv30_context.c | 4

Few comments below. On 10/16/2016 09:14 PM, Ilia Mirkin wrote: > This flips GM10x to using the updated format, which is what I tested > with. However GM20x and GP10x also use this TIC format. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nvc0_accel.c | 11 ++++++++++ > src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++ >

This series is to allow NVIDIA chips with shared memory to operate more efficiently (and to operate at all once we disable VRAM from the kernel driver) by allowing nouveau_screen to specify a domain to use for objects originally allocated into VRAM. If the domain is not overridden, the default NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be used in place of

Based on the original patch by Christoph Bumiller, but since it depends on kernel support patched I cannot push it yet. The changes are that I enable vblank by default, and offset takes OFFSET_HIGH/LOW instead of something relative to notifier_bo. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- diff --git a/man/nouveau.man b/man/nouveau.man index 7c72907..8765569

This series is to allow NVIDIA chips with shared memory to operate more efficiently (and to operate at all once we disable VRAM from the kernel driver) by allowing nouveau_screen to specify a domain to use for objects originally allocated into VRAM. If the domain is not overridden, the default NOUVEAU_BO_VRAM is used. A NV_VRAM_DOMAIN() macro is then introduced to be used in place of

New revision of this patchset that prevents VRAM objects from being allocated on VRAM-less systems like Tegra. This is required for Mesa to work on such systems. Changes since v2: - Use vram_size to detect systems without VRAM and set the correct domain instead of expecting each chip to set its domain explicitly. Alexandre Courbot (2): nouveau: support for custom VRAM domains nvc0: use

Are you sure this refactoring doesn't break anything? Few comments inline. On 10/27/2016 04:02 PM, Ilia Mirkin wrote: > This flips GM10x to using the updated format, which is what I tested > with. However GM20x and GP10x also use this TIC format. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nvc0_accel.c | 11 ++++++++++ > src/nvc0_accel.h |

nv30 seems to not support dma objects with offset, so simply extend the query_heap to cover the entire notifier, and use a offset in nv30_context_kick_notify. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- src/gallium/drivers/nouveau/nouveau_buffer.c | 14 +- src/gallium/drivers/nouveau/nouveau_context.h | 5 +

On Tue, Jun 17, 2014 at 2:34 AM, Maarten Lankhorst <maarten.lankhorst at canonical.com> wrote: > nv30 seems to not support dma objects with offset, so simply extend the query_heap to cover the > entire notifier, and use a offset in nv30_context_kick_notify. It would be great if you could detail the list of transformations that were done in the commit description, as well as what the

I believe I've addressed all the feedback from the first time around, and also made fixes necessary for GM20x based on testing results. I believe now it should actually work for all GM10x and GM20x. Further, GP10x should be very easy to add, but without someone to actually test I didn't want to claim support for it. Ilia Mirkin (7): exa: add GM10x acceleration support hwdefs: update

These are copied directly from the mesa repository. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++ src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++---------------- 2 files changed, 892 insertions(+), 340 deletions(-) create mode 100644 src/hwdefs/gm107_texture.xml.h diff --git

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/gallium/drivers/nouveau/nouveau_buffer.c | 4 +--- src/gallium/drivers/nouveau/nouveau_context.h | 1 - 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c b/src/gallium/drivers/nouveau/nouveau_buffer.c index e308ff4..904e2cc 100644 ---

Unfortunately there's only one RT_ARRAY_MODE setting for all attachments, so clears were previously truncated to the minimum number of layers any attachment had. Instead set the RT_ARRAY_MODE to 512 (the max number of layers) before doing the clear. This fixes gl-3.2-layered-rendering-clear-color-mismatched-layer-count. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> ---