similar to: LLVM IR source line error

On Tue, May 29, 2018 at 5:25 AM Muhui Jiang via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi > > I am using LLVM to help me do some code analysis. I wrote a LLVM Function > Pass to help me to generate some information. I use the code below to get > the source line information for every instruction. > > for (BasicBlock &BB : F){ > for(Instruction &I:

Hi David Thank you very much for your suggestions. ScopeLine works well. It could represent the start of a function. Do you know whether I can get the start column of this function? Many Thanks Regards Muhui 2018-05-30 3:25 GMT+08:00 David Blaikie <dblaikie at gmail.com>: > > > On Tue, May 29, 2018 at 5:25 AM Muhui Jiang via llvm-dev < > llvm-dev at lists.llvm.org>

Hi Paul Thanks for your comments. Suppose I can generate the control flow graph via LLVM Pass or the default option like '-dot-cfg' with opt. However, the control flow graph is based on llvm IR level. I would like to have a control flow graph based on binary level. Thus, I want to map the IR to binary address. As far as I know, we used to use the debug information to map the IR to source

Hi I know that LLVM provide some debug API for us to know the source code information. For example, every IR instruction's source line number and column number. However, are there any method to get a mapping from IR instruction to binary address directly. I don't want to use dwarf line mapping table as a bridge. I think the binary is generated by clang and llvm. I think there definitely

Hi However, frontend may also do various operations on the source code and one line number and column number could map to more than one binary address. Why LLVM IR cannot? Regrads Muhui 2018-06-12 23:18 GMT+08:00 mayuyu.io <admin at mayuyu.io>: > In theory that’s not exactly possible/accurate. Due to various operations > in the Backend like Instruction Legalization, one IR

I'm not familiar with the target instruction set, but if "MOV PC, R0" is not a return instruction, I'm guessing that the sequence starting at A39C is a dispatch through a jump table. The jump table would be considered part of the instruction stream and included in the scope of the line table. This is not a case where you would see end_sequence; my mistake. The line table does

There should be a line-table entry for the end of the function, which appears to be missing from the dump you provided. llvm-dwarfdump should report this address with 'end_sequence' in the Flags. Are you using a different dumper? I am not sure but my guess would be that inline data is not represented in the line table. The line table's primary purpose is to inform the debugger

Hi I write a LLVM function pass. The pass will loop the basicblock in the function, check the instruction's type with dyn_cast<switchinst>, print the instruction and the basicblock's successors. I think it is not very complex. My bitcode file is about 30M. My CPU is i7-7700(3.6GHz). It has been running for 60 hours but it is still running. I am not sure whether this is a normal

Hello everybody, On the documentation page for the tailcallelim pass you can read: "This pass transforms functions that are prevented from being tail recursive by an associative expression to use an accumulator variable, thus compiling the typical naive factorial or fib implementation into efficient code” However, I don’t see this behavior when trying to compile this variant of the

Considering F represents the function fputs_unlocked() in an LLVM pass, => F->isVarArg() returns true => F->getNumParams() returns 0 => *F returns declare i32 @fputs_unlocked(...) The signature of fputs_unlocked from man page is: int fputs_unlocked(const char *s, FILE *stream); Can anybody explain why fputs_unlocked() is recognized as a vararg method while it accepts two fixed

I'm trying to create a language structure that is a call to a function with a number of arguments that is only known at run time. I do this by using repeated indices to expand out a call with a single argument. However, when I change one of the arguments, all are changed. I don't see the same behavior when I initially create a call with multiple arguments. Even more strangely,

On Thu, Jan 26, 2012 at 3:41 PM, Hal Finkel <hfinkel at anl.gov> wrote: > On Thu, 2012-01-26 at 15:36 -0600, Sebastian Pop wrote: >> arm-none-linux-gnueabi > > Indeed, adding -ccc-host-triple arm-none-linux-gnueabi I also get Minor remark: please use -target instead of -ccc-host-triple that is now deprecated. Thanks for looking at this testcase. Sebastian -- Qualcomm

On Thu, 2012-01-26 at 15:36 -0600, Sebastian Pop wrote: > arm-none-linux-gnueabi Indeed, adding -ccc-host-triple arm-none-linux-gnueabi I also get vectorization (even though I don't get vectorization when targeting x86_64). I'll let you know what I find. -Hal -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory

Hi My goal is that given a binary and the corresponding input. I want to know what IR level basic blocks are covered. I need the detail information, which is the set of all the covered BBs rather than just a number. I want to know whether there are some tools that can support this requirements. If not, I think maybe instrumentation can helps. However, I do not know too much about this. Any

Hi paulr Thanks for your reply. Though DWARF info give me the code address ranges, there might be inline data. If so, how to handle this case? As for the dwarf line table. Sometimes, the source line might be zero. Do you know why? If all instructions should be describe in the line table, I think analyzing Dwarf line table is enough to get all the instructions addresses. Do you agree? I would

Hi I would like to use clang to cross compile the ARM binary. I hope the target binary contains both arm and thumb instruction sets. I use the flag -mhwdiv=arm,thumb. I compiled several binaries. However, I found that the thumb mode instructions are few. Even for very big program like gcc. The number of thumb mode instruction is less than 100. I get the ground truth from the mapping table.

Hi Nowadays I am using LLVM to do ARM binary analysis. I was wondering is llvm available to provide some debugging information on the mode of ARM. For example, llvm-dwarfdump could dump some instructions information for debugging. Is it able to know the mode for each instruction? Or we may write some llvm pass to help us to know the instruction mode? Any suggestions are welcomed. Many Thanks

Hi Muhui, I tried to grep the "DW_TAG_subprogram" from the debug_info . However, I noticed that the number I found is still less than the whole functions I found with LLVM IR. Do you have any experiences? Many Thanks The only explanation that comes to mind, is that the functions are not in the final binary object file. However, previously you said you believed they were present. If

Hi Alex Thanks for your email. But it seems not work. I removed the -fsanitize=address flag. The global buffer overflow message doesn't show. However, no *.sancov file is created after I run perlbench. Thus, I could not get the BB coverage. Do you have any ideas? Many Thanks Regards Muhui Alexander Potapenko <glider at google.com> 于2018年9月5日周三 下午7:14写道： > Hi Muhui, > > If

Hi I am using LLVM Pass combined with dwarf debug information to get all the function's start address. My steps are below: First, I write the function pass to get the start line of each function, which is finished. Then, based on the start line of every single function, I try to query the specific line from the dwarf's line binary table, which is generated with llvm-dwarfdump