similar to: About LowerEH_RETURN

Matt, Is this an example you are talking about: LoadedVect = DAG.getNode <http://llvm.org/docs/doxygen/html/classllvm_1_1SelectionDAG.html#ab02868bea897db34232413f1929ade1d> (ISD::INTRINSIC_WO_CHAIN <http://llvm.org/docs/doxygen/html/namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac771b9cda3b889242d457cc4d9b2159c>, dl, MVT::v4f64, DAG.getConstant

TableGen, as a DSL language, is made up of records. Every def corresponds to a record. For example, TableGen has a class Register, and your backend will define records by def GPR8 : Register<...>. You are correct in saying that the record definition is one of the SDNode values. These correspond 1:1 to llvm::ISD::NodeType

MachineRegisterInfo is maintaining a list of live-out registers for the MachineFunction. It contains the return value registers, and is typically created by XXXISelLowering::LowerReturn(). Various passes after instruction selection need to look at this list to determine which physical registers are live in return blocks. Eventually, the register allocators copy these live-out registers onto the

Matt, This seems to generate llvm.my_intrinsic just fine in the DAG, so no DAG errors; however, it won't match. For example, if I call the intrinsic from C, the DAG node looks to be named the same in dotty file but it won't match... am I missing something? I've done it exactly the way it was done above. The DAG looks great but it won't match. Did I miss something? Thanks.

On Fri, Jan 29, 2016 at 11:39 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > > On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com> > wrote: > >> Try visualising the DAG like this. >> >> ``` >> ---- GPR:$rA >> / >> set GPR:$rd ---- add >>

Hi, I'm planning to use Opus codec on a ARM cortex M7 device running at 400MHz. Con you please suggest the best configuration directives that I have to set in the config.h file in order to obtain the best perfromances on the cortex M7 architecture? Actually I have compiled libopus 1.2.1 with the following cnfiguration parameters: #define VAR_ARRAYS  1 #define FIXED_POINT  1 #define

Hi, I plan to implement a redundant Internet connection using BGP on 2 different Linux Routers. The routing daemon software I will be using is Zebra (zebra.org). I''m wondering if I should have my Linux firewall behind the 2 BGP routers, or could I keep the shorewall on both BGP routers? Has anyone had any experience with this? Any help is much appreciated. Thanks, Sam

Not the clearest of error messages. A successful cannot load. May 7 21:05:29 10.10.10.213 dovecot: child 21500 (login) returned error 89 May 7 21:05:29 10.10.10.213 dovecot: child 21501 (login) returned error 89 May 7 21:05:29 10.10.10.213 dovecot: child 21502 (login) returned error 89 May 7 21:05:29 10.10.10.213 dovecot: child 21503 (login) returned error 89 May 7 21:05:29 10.10.10.213

Matt, Thanks for the response. Is there an example in the code somewhere of doing the intrinsic ID method? I don't need to put it a lot of places so I'm not sure it warrants adding a node. Thanks. On Tue, Feb 2, 2016 at 12:35 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > On Feb 2, 2016, at 09:29, Ryan Taylor via llvm-dev < > llvm-dev at lists.llvm.org>

Tried that. It rebuilds index based on dovecot-uidlist. But not the dovecot-uidlist based on actual mail data. :( Fil On March 21, 2018 11:58:21 PM EDT, "@lbutlr" <kremels at kreme.com> wrote: >On 2018-03-21 (17:15 MDT), Dmitry Filonov ><filonovd at enders.tch.harvard.edu> wrote: >> Now the question is if there's any way to tell dovecot to rebuild

Hello, Could someone please explain the semantics of TargetOpcode::KILL? Specifically, in this example, which register is killed? Would it be legal for operands 0 and 1 to refer to different registers? 128B %R3<def> = KILL %R3, %R3_1<imp-use>, %R3_23<imp-use> (In my out-of-tree target, %R3 is a <4xi32> register, %R3_1 is an i32 sub-register of %R3, and %R3_23 is

Hi, I was wondering if there is a way with llvm-lit and FileCheck to identify if a specific test should run or not based on the processor architecture. For example, I have a test that can run only in an Intel KNL, so if I run the tests in a Sandybridge I want to ignore that test. Any idea? Thanks! Simone ----------------------------------------------------------------------------------- This

Hello, Is there a way to dump the Module IR with the SCEV as comment at the end of each line? The -analyze or -debug-pass is not printed on the IR itself. Maybe through the DiagnosticInfo? -- *Alexandre Isoard* -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180322/e178b4c8/attachment.html>

Hi In the case where you have access to TCP and UDP outbound initiated connections and no choice of the port numbers due to the firewall setup it would be very useful to be able to specify both the UDP and TCP ports that tinc uses separately. Currently in 1.0 I end up with a TCP based VPN because I can't tell tinc which UDP port to connect to the remote side on. Could this be added to 1.1?

The new @llvm.memcpy API does not have an alignment parameter. Instead the docs say to use the align <n> attribute. How is this supposed to work with different alignments? For example, I have one memcpy with align 4, align 4, and another with align 1, align 1. ; Function Attrs: argmemonly nounwind declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly align 4, i8* nocapture

Hi there, I think this bug, I have found recently, seems to be not trivial: https://bugzilla.redhat.com/show_bug.cgi?id=1558507 In my opinion, it is a violation against the WORM defintion. Discussions are welcome ;-) Regards David Spisla -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, It's been a little while, but I'd like to include a paper that uses and extends LLVM for more precise and declarative dynamic taint-tracking: Compiler-instrumented, Dynamic Secret-Redaction of Legacy Processes for Attacker Deception Frederico Araujo, Kevin W. Hamlen *Proceedings of the 24th USENIX Security Symposium, August* 2015. Link:

Hello, In MachineFrameInfo::print (llvm-6.0.0) line 235, when printing SP offsets, shouldn't it be // -> consider stack growth direction int64_t Off = StackGrowsDown ? SO.SPOffset - ValOffset : SO.SPOffset + ValOffset; Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hello, I have a CallInstr for "functionA". I renamed it to "functionB" but I want to decrease number of arguments as functionA accepts e.g two and functionB just one. So far, I dont find any function to just replace args / set args size. Any idea? Maybe other solution... Is there any way to create a new CallInstr for functionB, copy things from CallInstr of functionB a copy

Hi dear OpenBSD users, There is an early UBSan support for OpenBSD. Have already planned improvements (and will start looking what can be ported which in the case of OpenBSD won t be a lot) but at least there is a basis :-) Kind regards. -------------- next part -------------- An HTML attachment was scrubbed... URL: