similar to: Run llc with -debug flag

llc accepts all the -debug variants when built with asserts (or debug build). It will accept -debug as well as -debug=prologepilog for your case. On Wed, Mar 21, 2018 at 7:27 AM, Meet Udeshi via llvm-dev < llvm-dev at lists.llvm.org> wrote: > I want to check debug output of "PrologEpilogInserter" machine pass, and I > have seen in the code that there are various `DEBUG`

On 6/24/20 11:21 AM, Matt Arsenault via llvm-dev wrote: > > >> On Jun 24, 2020, at 14:13, Arthur Eubanks via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hi, >> >> As part of new pass manager work, I've been trying to get something >> like `opt -foo` working under the NPM, where `foo` is

> On Jun 24, 2020, at 19:17, Arthur Eubanks <aeubanks at google.com> wrote: > > > > On Wed, Jun 24, 2020 at 12:23 PM Philip Reames <listmail at philipreames.com <mailto:listmail at philipreames.com>> wrote: > > > On 6/24/20 11:21 AM, Matt Arsenault via llvm-dev wrote: >> >> >>> On Jun 24, 2020, at 14:13, Arthur Eubanks via

Hi, As part of new pass manager work, I've been trying to get something like `opt -foo` working under the NPM, where `foo` is the name of a pass. In the past there's been no reason to keep the names of passes consistent between NPM and legacy PM. But now there is a reason to make them match, so that we don't have to touch every single test that uses `opt`. There are a couple of

Hi all, We've seen several examples recently of performance opportunities on POWER if we can improve the location of save/restore code for callee-saved registers. Both Nemanja and myself have discussed this with several people, and it seems that there are two possibilities for improving this: 1. Extend shrink wrapping to make the analysis of callee-saved registers more precise. 2.

Hi Dale, yes it's just stack alignment. Unfortunately your patch doesn't make any difference. Thanks for thinking about this, Duncan. On Friday 27 June 2008 19:51:00 Dale Johannesen wrote: > On Jun 27, 2008, at 3:11 AMPDT, Duncan Sands wrote: > > FAIL: test/CodeGen/X86/vec_shuffle-10.ll > > Failed with exit(1) at line 3 > > while running: llvm-as <

On Jun 27, 2008, at 3:11 AMPDT, Duncan Sands wrote: > FAIL: test/CodeGen/X86/vec_shuffle-10.ll > Failed with exit(1) at line 3 > while running: llvm-as < test/CodeGen/X86/vec_shuffle-10.ll | llc - > march=x86 -mattr=+sse2 | not grep {sub.*esp} > subl $16, %esp > subl $16, %esp > child process exited abnormally Is the code actually loading and storing

On Jun 30, 2008, at 9:25 AMPDT, Duncan Sands wrote: > Hi Dale, yes it's just stack alignment. Unfortunately > your patch doesn't make any difference. > > Thanks for thinking about this, > > Duncan. OK, the test is not quite right then. This doesn't happen on Darwin so I'm afraid you'll have to debug it. Perhaps testing for

Hi Dale, > OK, the test is not quite right then. This doesn't happen on Darwin > so I'm > afraid you'll have to debug it. Perhaps testing for > (RegInfo->needsStackRealignment(Fn) && > FFI->getObjectIndexEnd()!=0) > ? yes, that works - thanks! Since I have no idea what this is doing, is it ok if I leave it to you to commit it?

Hi all, Virtual ISAs such as WebAssembly and NVPTX use infinite virtual register sets instead of traditional phsyical registers. PrologEpilogInserter is run after register allocation and asserts that all virtuals have been allocated but doesn't otherwise depend on this if scavenging is not needed. We'd like to use the target-independent PEI code for WebAssembly, so we're proposing a

Hi Matthias, I am a fourth year undergraduate student with some knowledge working on code generation, but with the java backend (committer at an Apache project) and have C++ as my primary language. What I've done so far? ----- 1. I've created an account on bugzilla 2. studying LLVM ProgrammersManual 3. studying LLVM CodingStandards Help ---- 1. trying to setup `llvm-core` and `clang`

> On Dec 10, 2015, at 10:49 AM, Derek Schuff <dschuff at google.com> wrote: > > > > On Thu, Dec 10, 2015 at 10:13 AM Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: > > I am tempted to think no, we don’t, but I don’t know the use cases. > What post-RA passes with want to run with virtual regs? > > The immediate

On Tue, May 12, 2009 at 11:55 PM, Chris Lattner <clattner at apple.com> wrote: > Dan, can you add IVUsers.cpp to the appropriate cmakefile? > > -chris > > > On May 12, 2009, at 10:54 PM, OvermindDL1 wrote: > >> On Tue, May 12, 2009 at 11:40 PM, Chris Lattner <clattner at apple.com> >> wrote: >>> >>> On May 12, 2009, at 10:24 PM,

On 6/15/2018 11:58 AM, Muhui Jiang wrote: > Is it possible to dump both the frame setup/cleanup MIR and the MIR I > have at this moment? You can dump the MIR after each pass with -mllvm -print-after-all. Look for "Prologue/Epilogue Insertion". -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Hi Evan, Thanks for your feedback! 2009/1/7 Evan Cheng <evan.cheng at apple.com>: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > > > As you can see, PrologEpilogInserter has inserted at the beginning > of the function some code for manipulation of the frame pointer and > this inserted code uses the LR register. > As far as I understand,

Running on x86-64 linux: FAIL: test/CodeGen/X86/vec_ins_extract.ll Failed with exit(1) at line 1 while running: llvm-as < test/CodeGen/X86/vec_ins_extract.ll | opt -scalarrepl -instcombine | llc -march=x86 -mcpu=yonah | not grep sub.*esp subl $16, %esp subl $16, %esp subl $16, %esp subl $16, %esp child process exited abnormally FAIL:

Hi, everyone, I'm currently the code owner for the PowerPC target. I worked on the PowerPC target for many years, and that was a lot of fun, but I've not been directly involved in development for PowerPC for some time. I would like to nominate Nemanja Ivanovic for the role of PowerPC target code owner. Insofar as a code owner is responsible for making sure that patches are reviewed,

On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > > > As you can see, PrologEpilogInserter has inserted at the beginning > of the function some code for manipulation of the frame pointer and > this inserted code uses the LR register. > As far as I understand, ARMRegisterInfo.td should exclude the LR > register from the set of allocatable registers for functions that

On Thu, Apr 9, 2009 at 4:34 PM, Anton Korobeynikov <anton at korobeynikov.info>wrote: > Hello, Aaron > > > How/where are function prologs and epilogs generated, is it bespoke C++ > code > > or TableGen generated ? > > > > If someone could point me in the right direction please. > Calling convention is really-really far from prologue/epilogue emission :)

> On Dec 10, 2015, at 9:39 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > > > ----- Original Message ----- >> From: "Quentin Colombet" <qcolombet at apple.com> >> To: "Derek Schuff" <dschuff at google.com> >> Cc: "Hal Finkel" <hfinkel at anl.gov>, llvm-dev at lists.llvm.org >> Sent: Wednesday, December