similar to: Remap values in PromotedFloats

Displaying 20 results from an estimated 2000 matches similar to: "Remap values in PromotedFloats"

2018 Mar 09
2
[SelectionDAG] DbgValue nodes aren't transferred
Hi, I have a problem that dbg_value nodes are not transferred when integer DAG nodes are promoted. For example, an i32 add node is promoted to a i64 add node by DAGTypeLegalizer::PromoteIntegerResult and its dbg_value node is not transferred to the new node. t9: i32 = add nsw t5, t8 --> t31: i64 = add t30, t7 ; the dbg_value node is not transferred to the new i64 add node. For expansion,
2018 Mar 09
0
[SelectionDAG] DbgValue nodes aren't transferred
+ Adrian, Joshua + Jonas, since he contributed the transferDbgValues change in DAGTypeLegalizer::SetExpandedInteger > On Mar 8, 2018, at 5:44 PM, Se Jong Oh via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > I have a problem that dbg_value nodes are not transferred when integer DAG nodes are promoted. For example, an i32 add node is promoted to a i64 add node by
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
> so I think we need to use non-extending load for element size less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly. > if (N->getOperand(0).getValueType().getVectorElementType().getSizeInBits() < 8) { > return DAG.getLoad(N->getValueType(0), dl, Store, StackPtr, MachinePointerInfo()); > } else { > return
2018 Mar 13
2
[SelectionDAG] DbgValue nodes aren't transferred
Thanks for help! I think that sign extension is not involved here. PromoteIntegerResult is called since i32 is not a legal type in my target and the legalizer promotes operations with i32 result type to i64 operations. I think that SetPromotedInteger seems to be a common place for all promotions like SetExpandedInteger. Jonas, I would appreciate it if you can guide me about whether my
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
Please open a bugzilla ticket and attach your testcase. It will allow us to debug and fix the problem. Thanks - Elena From: JinGu [mailto:jingu at codeplay.com] Sent: Saturday, September 16, 2017 00:38 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at
2016 Jan 25
1
Return value from TargetLowering::LowerOperation?
Hi, On 01/22/2016 05:02 PM, Tom Stellard wrote: > On Fri, Jan 22, 2016 at 01:58:49PM +0100, Mikael Holmén via llvm-dev wrote: >> Hi, >> >> I'm a litle bit puzzled by the TargetLowering::LowerOperation function, >> and what different callers of this function assumes about the returned >> value. >> > SelectionDAGLegalize::LegalizeOp() is your best
2018 Mar 14
0
[SelectionDAG] DbgValue nodes aren't transferred
Hi Sejong, Indeed, I think you are right and we should call transferDbgValues in SetPromotedInteger. I couldn’t immediately find a suitable in-tree test to verify this though. Can you check and let me know whether this works for your target? Thanks, Jonas > On Mar 13, 2018, at 7:45 PM, Se Jong Oh <sejooh at microsoft.com> wrote: > > Thanks for help! I think that sign extension
2013 Mar 05
4
[LLVMdev] Vector splitting vs widening
Hello, Working on my (currently out-of-tree) BG/Q PPC enhancements, I've run into the following problem with vector type legalization. Here's a quick example: Scalarize node result 0: 0x2348420: v1f32 = extract_subvector 0x23434a0, 0x2348320 [ID=0] Scalarize node result 0: 0x2348220: v1f32 = extract_subvector 0x23434a0, 0x23466e0 [ID=0] Split node result: 0x23469e0: v4f32 =
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
> extends the elements to 8bit and stores them on stack. Store is responsible for zero-extend. This is the policy... - Elena -----Original Message----- From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Friday, September 15, 2017 17:45 To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com Subject: Re: Question
2013 Mar 05
0
[LLVMdev] Vector splitting vs widening
Hi Hal, On 05/03/13 18:50, Hal Finkel wrote: > Hello, > > Working on my (currently out-of-tree) BG/Q PPC enhancements, I've run into the following problem with vector type legalization. Here's a quick example: > > Scalarize node result 0: 0x2348420: v1f32 = extract_subvector 0x23434a0, 0x2348320 [ID=0] > > Scalarize node result 0: 0x2348220: v1f32 = extract_subvector
2016 Jan 22
3
Return value from TargetLowering::LowerOperation?
Hi, I'm a litle bit puzzled by the TargetLowering::LowerOperation function, and what different callers of this function assumes about the returned value. In several places it seems like it is assumed that LowerOperation can return three kinds of values: * Something completely new. * SDValue() * The same SDValue as LowerOperation was called on. However in some places, e.g. in
2018 Mar 14
2
[SelectionDAG] DbgValue nodes aren't transferred
Hi Jonas, Thanks for taking a look! It makes linear-dbg-value.ll pass for my target by producing DEBUG_VALUEs correctly. I also tried a simple function with few operations and confirmed DEBUG_VALUEs which are not produced without trasferDbgValues in SetPromotedInteger. Thanks, Sejong From: jdevlieghere at apple.com <jdevlieghere at apple.com> Sent: Wednesday, March 14, 2018 4:07 AM To: Se
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
Hi All, I have a question about splitting 'EXTRACT_VECTOR_ELT' with 'v2i1'. I have a llvm IR code snippet as following: llvm IR code snippet: for.body: ; preds = %entry, %for.cond %i.022 = phi i32 [ 0, %entry ], [ %inc, %for.cond ] %0 = icmp ne <2 x i32> %vecinit1, <i32 0, i32 -23> %1 = extractelement <2 x i1>
2012 Mar 23
2
[LLVMdev] Fixing VAARG on PPC64
On Fri, 23 Mar 2012 09:50:12 +0100 Ivan Llopard <ivanllopard at gmail.com> wrote: > Hi Finkel, > > Le 23/03/2012 05:50, Hal Finkel a écrit : > > The PowerPC backend on PPC64 for non-Darwin (SVR4 ABI) systems > > currently has a problem handling integer types smaller than 64 bits. > > This is because the ABI specifies that these types are > > zero-extended
2010 Sep 22
2
[LLVMdev] r114523 (convert the last 4 X86ISD...) breaks clang
Hello, After commit r114523, I start to get crash when compiling with clang (Release+Asserts) for i386: (I know I should fill a bug report instead of posting here, but I don't get much time right now). Trying to compile the following simple code, clang asserts. ---------- round.c -------- #include <math.h> float test() { return llround(1); } -------------------- [MacPro:~/Desktop]
2012 Mar 23
0
[LLVMdev] Fixing VAARG on PPC64
Hi Finkel, Le 23/03/2012 05:50, Hal Finkel a écrit : > The PowerPC backend on PPC64 for non-Darwin (SVR4 ABI) systems > currently has a problem handling integer types smaller than 64 bits. > This is because the ABI specifies that these types are zero-extended to > 64 bits on the stack and the default logic provided in LegalizeDAG does > not use that convention. Specifically, for
2012 Jan 11
1
[LLVMdev] widen_load fails on AVX
Hello Chris, We caught this failure: ./llc -mattr=+avx ../../test/CodeGen/X86/widen_load-2.ll llc: LegalizeTypes.cpp:831: void llvm::DAGTypeLegalizer::SetSplitVector(llvm::SDValue, llvm::SDValue, llvm::SDValue): Assertion `Lo.getValueType().getVectorElementType() == Op.getValueType().getVectorElementType() && 2*Lo.getValueType().getVectorNumElements() ==
2018 Mar 15
1
[SelectionDAG] DbgValue nodes aren't transferred
> On Mar 14, 2018, at 7:55 PM, Se Jong Oh <sejooh at microsoft.com> wrote: > > Hi Jonas, > > Thanks for taking a look! It makes linear-dbg-value.ll pass for my target by producing DEBUG_VALUEs correctly. I also tried a simple function with few operations and confirmed DEBUG_VALUEs which are not produced without trasferDbgValues in SetPromotedInteger. That’s great news! Do
2012 Aug 16
1
[LLVMdev] DAGTypeLegalizer::RemapValue failure
Hi, If you are familiar with LegalizeTypes I will be glad if you can help me with the following scenario. I'm debugging some ll test that fails with an assertion in "void DAGTypeLegalizer::RemapValue(SDValue &N)" because it does not expect that a remap to a new node exists. However looking at the code for a while this seems to be a valid case. I see that many times nodes are
2010 Sep 22
0
[LLVMdev] r114523 (convert the last 4 X86ISD...) breaks clang
I will take a look in the next couple hours. Feel free to revert it in the meantime, thanks! -Chris On Sep 22, 2010, at 1:53 AM, Jean-Daniel Dupas <devlists at shadowlab.org> wrote: > Hello, > > After commit r114523, I start to get crash when compiling with clang (Release+Asserts) for i386: > (I know I should fill a bug report instead of posting here, but I don't get