similar to: Encoding an X86 format with long operands

Hi Gus, When you say "n byte destination" you mean you want to encode an n byte address as a constant within the instruction? That would mean you couldn't encode an address that comes from a register. ~Craig On Tue, Mar 20, 2018 at 9:48 AM, Gus Smith via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi all. > > tl;dr: I would like to add a long x86 instruction

Whoops - sorry for the confusion. n would be set in stone beforehand. I basically meant to indicate that we'd either be looking at a 32 bit or 64 bit system, ie 4 byte or 8 byte addresses. On Tue, Mar 20, 2018, 1:07 PM Craig Topper <craig.topper at gmail.com> wrote: > Hi Gus, > > When you say "n byte destination" you mean you want to encode an n byte > address as

That wasn't the part that confused me. What confused me was what you expected to be encoded into the instruction. Your math indicated that you multiple n by 3 and added 1 to it to get your 13 bytes. So that means you intend to use 4 bytes to store an address in 32 bits which implied to me that you intended to have a fixed address encoded. But what if the address in in a register as would often

ASM is the text output you want printed in a textual listing of the assembly. The curly braces you see in some text strings like "adcx{l}\t{$src, $dst|$dst, $src}" are there to provide different operand orders for at&t syntax vs intel syntax. Anything after $ matches the name in the outs/in part of the instruction. IIC_SSE_PREFETCH is part of the scheduler system to provide

Great info -- all of this has been incredibly useful. Do you have any links to the documentation from this, or does it just come from your experiential knowledge? FYI, I achieved what I set out to achieve when I wrote this email. I'm moving on to a more complex goal now, but the original question was answered completely, in my opinion. This was the key line: def CACHEOP : I<0x06, RawFrm,

Craig, thanks for the quick response. That helps a lot. I had no clue they were buried in there, though I guess I should have looked harder -- the hex should have given me a clue, perhaps! For the sake of my own edification (and not taking up too much of your time) I will try to generate it myself. I've found the definition of the "I" class at line 358 of

Hello all. LLVM newbie here. If anything seems glaringly wrong with my use of LLVM, that's probably why. Here's what I'm trying to do. I have modified the gem5 simulator to accept a "new" x86 instruction. I've done this by just reserving the opcode in gem5's ISA specification, just as all other instructions are specified. I'm trying to get an LLVM backend to

Here's a couple examples for mapping an intrinsic to an X86 instruction from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can find others. let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],

Hi all -- first time poster, hoping that this is going to the right list. Also a complete LLVM newbie, so please correct any glaring errors in my understanding. I am an architecture researcher at Penn State working on Processing in Memory (PIM) architectures. Currently, I plan to use LLVM to detect and replace groups of instructions which can be accelerated in memory. Once a group of

Hi All, I'm trying to compile clang+llvm on my desktop with cross-compiler to be able to work with llvm commands in ubuntu-arm image whithin gem5. If anybody has done this before I'd be so thankful to know the exact process and commands. I tried to configure llvm as follows but I couldn't get the arm-arm version correctly. To sum up, I need to cross-compile llvm for ARM to work in

Hi, I am trying to optimize some benchmarks using LLVM and run them on gem5 simulator (build for ARM). I am using Sourcery Codebench cross-compiler for ARM on my x-86 machine. My steps up till now have been using the following commands. 1. clang -static -emit-llvm -march=armv7-a -mfloat-abi=soft -target arm-elf a.cpp -c -integrated-as \

Purpose: I implemented a pass on LLVM backend that changes the output format of *ARM* assembly/binary (e.g add a jump at the end of each basic block to eliminate fall through). By calling: llc -march=arm somefile.bc it generates expected arm assembly/binary that runs properly on arm gnu linux (I use qemu-arm and gem5 to simulate it). Now I want to do the same thing on standard c library, but

>> > It is done. Then, I should copy this version on my image and then boot >> > the image with gem5. The >> > problem is when I try to run llvm-commands in gem5, they don't work and >> > said : "cannot execute binary file". >> What does "file" says on the binary? > when I use commands like : "#arm-linux-gnueabi-clang test.c

Hi all, I'm trying to simulate an extended x86 architecture on gem5 with several new instructions. My hardware setup is done and now I'd like llvm to accept the existence of the new instruction passed in inline assembly and output the correct opcode and registers. I chose the two-byte opcode 0x0F 0x7A and I would like the instruction to have the same operands and return values as CVTPS2PI

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

> It is done. Then, I should copy this version on my image and then boot the image with gem5. The > problem is when I try to run llvm-commands in gem5, they don't work and said : "cannot execute binary file". What does "file" says on the binary? > This means that I couldn't cross-compile the llvm for ARM to work on ARM! Something is broken on your side. I can

tl;dr, I'd like to add my own instruction, but I'm running into problems due to my lack of x86 encoding/decoding understanding. Hello all. Currently, I'm working on adding my own x86 instruction. I have done this once before; the basic process I used was: 1. Find an unused opcode, e.g. 0xF1 in this table: http://ref.x86asm.net/coder32.html 2. Insert an instruction into

> > FWIW, I build baremetal newlib for arm-eabi using clang, and it works. I >> had to patch a few of the __attribute__((naked)) functions because they >> were using pre-UAL asm syntax, but for the most part it "just works". >> > I build the baremetal newlib using arm-none-eabi-gcc as well, but after linking with the hello world program, it failed to run on

Hi Silky, If I got correctly, you seem to be trying to run a bare-metal image on your model, but you compile with linux-gnueabi GCC. I don't know if that will make a difference, but I'd try to use none-eabi GCC toolchain and set the -target armv7a-none-eabi just in case. On 10 March 2013 00:26, Silky Arora <silkyar at umich.edu> wrote: > Most of the search results talk about

Thanks Renato and Giang. I was able to run a simple HelloWorld program on gem5 (in SE mode) by using -target -arm-none-linux-gnueabi as the option during cross compilation. I am trying to cross compile some Computer Vision algorithms, which use OpenCV libraries, and I tried using the same command line options - clang++ *-emit-llvm -static -c -Wall -g -O0 -mfpu=vfp -mfloat-abi=soft