similar to: MIR YAML deserialisation failure

Valentin, in terms of limitations as Sean pointed out, an important one is that .mir doesn't have MachineFunctionInfo which may result in failure on accesses to global variables due to use of register X2. The verifier considers it an undefined register. Also, it's probably easier to reduce test cases using bugpoint starting from an IR test case. With the code you provided, I get a

Hello Valentin, To generate a mir test case i think the process is to first create an IR file by passing '-S -emit-llvm' to clang, then you can feed that file into llc and use stop-before to get the mir just before the if-converter pass, eg: `llc -stop-before=if-converter -simplify-mir -o test.mir test.ll`. Also there is a MIR language reference: https://llvm.org/docs/MIRLangRef.html

Thank you both! I was running into the issue that bugpoint was reducing my test-case into other failures and I hadn't managed yet to find the right point in the Julia pass pipeline to insert the module to reproduce the issue reliably from llc and that's why I started looking at using the MIR. I will go back at looking at the pass pipeline and the IR and get a reproducer that way!

I'm not sure if this helps, but here it is in case it does. I typically use bugpoint in a way as to keep the actual failure that I'm after. For example, with the test case you've pasted, I was looking for a specific assert. So I used bugpoint this way: $ cat reduceme.sh #!/bin/bash llc -filetype=obj $1 2>&1 | grep 'Cannot lower calls with arbitrary operand bundles'

In our fork of LLVM we often need to reduce a crash testcase for a specific assertion. After writing lots of "only give me this specific assertion" scripts like the above I decided to write a script that automates all this for me: <https://github.com/CTSRD-CHERI/clang/blob/master/utils/creduce_crash_testcase.py>. (It's called creduce_crash_test.py but it will actually use

I am confused about the rules for when upper and lower case letters should be used in MIR. As an example our downstream target has upper case letters in its sub-register indices and as a result we cannot import exported MIR without manually 'lower casing' it first which is obviously rather annoying. Looking in https://llvm.org/docs/MIRLangRef.html it is stated that instruction names are

Dear LLVM developers, Just as LLVM IR can be read/write via persistent bitcode (*.bc *.ll) files, is there any similar implementation in LLVM to read/write Machine IR (MIR) via a persistent file? If not and I would like to add it (e.g. for ARM or RISC-V), could you direct me materials and/or LLVM source code modules where I should start with? Best Regards, Lele Ma -------------- next part

Hi everyone, I'm quite new to LLVM *and doing a Q-learning *(*just a hobby*)* on register allocation for LLVM. RegAllocRL is based on* *RegAllocBase*,* RegAllocBasic and add some feature to implement Q-learning algorithm. * *I*’*ve currently run as MachineFunctionPass and things seem to work in simple case. In order to make progress on training*, *I have questions and want to get some

On 6/15/2018 11:58 AM, Muhui Jiang wrote: > Is it possible to dump both the frame setup/cleanup MIR and the MIR I > have at this moment? You can dump the MIR after each pass with -mllvm -print-after-all. Look for "Prologue/Epilogue Insertion". -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Hi llvm developers, I might be overlooking something, but I think the ARMConstantIsland pass uses the wrong size for the MachineInstrs representing jump tables: Currently, there is the following calculation in doInitialJumpTablePlacement (lib/Target/ARM/ARMConstantIslandPass.cpp:588): ---------------------------------------------------------------------- unsigned Size = JT[JTI].MBBs.size() *

Hi Matthias, Thanks a lot for the project. Could you put it in the google doc below? I'd appreciate if you could follow more-or-less the format. Are you going to be the mentor. Cheers, Vassil On 06/02/17 19:29, Matthias Braun wrote: > Here's another one: > > = Improve code generation testing = > > After instruction selection LLVM uses the MI (Machine Instruction)

Hi all, The CodeGen library is a big bag of interdependent bits. This caused a circular dependency in the MIR serialization commit (r237954), which got reverted in r238007. I propose separating the machine IR out of CodeGen and into its own MIR library, living at lib/MIR. This touches every target but it's mostly a mechanical change that renames the header files, although a couple of

Hi folks, Happy new year! Last LLVM Developers' Meeting I had a BoF: 'Raising Next Generation LLVM Developers'. It was suggested that we should update our open projects page and possibly restructure it a little bit. I volunteered to do this work and I need your help. Chandler and I started working on a google doc [1]. We pinged few code owners asking them to list of

Dear LLVM developers, My goal is to write LLVM Machine IR (MIR) passes to analyze the assembly source code. But it seems I need to find a way to translate the handwritten assembly code into MIR format first. Is there any materials, or any modules in LLVM source code, that can help to translate assembly code into LLVM MIR for analysis? Or is there any easier ways to analyze assembly code in MIR

Hi, My name is Puyan and I've been exploring ways to improve the state of instruction level diffing using llvm and MIR. Below is a proposal for a new llvm tool meant to address issues encountered when diffing at the machine level. I'm eager to hear the community's feedback. Thanks PL mir-canon: A new tool for canonicalizing MIR for cleaner diffing. Problem Statement and

Llvm-mctoll will raise a binary back to LLVM IR. Not exactly what you want but it might be something you can leverage. https://github.com/microsoft/llvm-mctoll On Mon, Nov 25, 2019 at 1:19 PM Nicolai Hähnle via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On Thu, Nov 21, 2019 at 3:37 AM Lele Ma via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > My goal is to write

In light (pun not intended) of the announcement here https://wiki.ubuntu.com/MirSpec what does this mean for LightDM being a viable free desktop display manager. The diagram shows the system compositor as being launched by LightDM in much the same way X is, and the plan looks very much like what we would do for Wayland. Is MIR going to be a hard dependency? Is Wayland support going to be dropped

> On May 26, 2015, at 1:37 PM, Duncan P. N. Exon Smith <dexonsmith at apple.com> wrote: > >> >> On 2015-May-26, at 09:46, Alex L <arphaman at gmail.com> wrote: >> >> Hi all, >> >> The CodeGen library is a big bag of interdependent bits. This caused >> a circular dependency in the MIR serialization commit (r237954), which got >>

Hi all, After a recent upstream merge into our downstream sources we are suddenly encountering the freeze instruction in LLVM IR for div/rem pairs. This seems to be related to [1]. Our downstream target is GlobalISel only and unfortunately GlobalISel doesn't support this instruction yet, so most of our internal test-suite is now breaking due to GlobalISel not being able to translate this

Hi A few of us have discussed enhancing the MIR vregs to include support for named-vregs. At the moment named regs are only supported for physical registers and number regs are reserved for vregs. We've decided that to properly implement a syntax for MIR named vregs we first need to reorganized the sigils used for physical registers and external symbols so our proposal is to swap the sigil