similar to: Generating a custom opcode from an LLVM intrinsic

Displaying 20 results from an estimated 2000 matches similar to: "Generating a custom opcode from an LLVM intrinsic"

2018 Mar 19
4
Generating a custom opcode from an LLVM intrinsic
Craig, thanks for the quick response. That helps a lot. I had no clue they were buried in there, though I guess I should have looked harder -- the hex should have given me a clue, perhaps! For the sake of my own edification (and not taking up too much of your time) I will try to generate it myself. I've found the definition of the "I" class at line 358 of
2018 Mar 19
0
Generating a custom opcode from an LLVM intrinsic
ASM is the text output you want printed in a textual listing of the assembly. The curly braces you see in some text strings like "adcx{l}\t{$src, $dst|$dst, $src}" are there to provide different operand orders for at&t syntax vs intel syntax. Anything after $ matches the name in the outs/in part of the instruction. IIC_SSE_PREFETCH is part of the scheduler system to provide
2018 Mar 18
0
Generating a custom opcode from an LLVM intrinsic
Here's a couple examples for mapping an intrinsic to an X86 instruction from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can find others. let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
2018 Mar 20
1
Generating a custom opcode from an LLVM intrinsic
Great info -- all of this has been incredibly useful. Do you have any links to the documentation from this, or does it just come from your experiential knowledge? FYI, I achieved what I set out to achieve when I wrote this email. I'm moving on to a more complex goal now, but the original question was answered completely, in my opinion. This was the key line: def CACHEOP : I<0x06, RawFrm,
2018 Mar 20
2
Encoding an X86 format with long operands
Hi all. tl;dr: I would like to add a long x86 instruction which doesn't conform to any existing format that I know; I'm not sure where to start. I am attempting to add an instruction into X86, to be simulated in gem5. I've already added a simple, opcode-only instruction which I can successfully decode and run in gem5, so I am roughly familiar with .td files and how backends are built
2018 Mar 20
2
Encoding an X86 format with long operands
Whoops - sorry for the confusion. n would be set in stone beforehand. I basically meant to indicate that we'd either be looking at a 32 bit or 64 bit system, ie 4 byte or 8 byte addresses. On Tue, Mar 20, 2018, 1:07 PM Craig Topper <craig.topper at gmail.com> wrote: > Hi Gus, > > When you say "n byte destination" you mean you want to encode an n byte > address as
2014 Apr 16
2
[LLVMdev] X86 mmx movq disassembler fail
0x0f 0x6f 0xc8 And 0x0f 0x7f 0xc1 Should both be movq % mm0, % mm1. (AT&T) However, llvm 3.4 at least does not recognise the second variant as being a valid instruction. We are currently compiling up latest src incase it has been fixed. If not, could someone take a look or recommend how to fix? Lee -------------- next part -------------- An HTML attachment was scrubbed... URL:
2018 Mar 20
0
Encoding an X86 format with long operands
Hi Gus, When you say "n byte destination" you mean you want to encode an n byte address as a constant within the instruction? That would mean you couldn't encode an address that comes from a register. ~Craig On Tue, Mar 20, 2018 at 9:48 AM, Gus Smith via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi all. > > tl;dr: I would like to add a long x86 instruction
2015 Mar 24
3
[LLVMdev] [PATCH] fix outs/ins of MOV16mr instruction (X86)
Hi, This patch fixes outs/ins of MOV16mr instruction of X86. Thanks. diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index e9a0431..f5b2064 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -1412,7 +1412,7 @@ let SchedRW = [WriteStore] in { def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
2018 Mar 20
0
Encoding an X86 format with long operands
That wasn't the part that confused me. What confused me was what you expected to be encoded into the instruction. Your math indicated that you multiple n by 3 and added 1 to it to get your 13 bytes. So that means you intend to use 4 bytes to store an address in 32 bits which implied to me that you intended to have a fixed address encoded. But what if the address in in a register as would often
2017 Sep 30
2
invalid code generated on Windows x86_64 using skylake-specific features
I have this code, which works fine on MacOS and Linux hosts: const char *target_specific_cpu_args; const char *target_specific_features; if (g->is_native_target) { target_specific_cpu_args = ZigLLVMGetHostCPUName(); target_specific_features = ZigLLVMGetNativeFeatures(); } else { target_specific_cpu_args = ""; target_specific_features =
2017 Oct 01
1
invalid code generated on Windows x86_64 using skylake-specific features
I suspect that there are 2 issues here: * I have incorrect alignment somewhere * MSVC / .pdb / CodeView debugging is not working correctly. I think the latter would help solve the former. I will send out a new email later talking about the issues I'm having debugging llvm-generated binaries with MSVC. On Sat, Sep 30, 2017 at 3:33 PM, Andrew Kelley <superjoe30 at gmail.com> wrote:
2018 Feb 21
1
Finding and replacing instruction patterns
Hi all -- first time poster, hoping that this is going to the right list. Also a complete LLVM newbie, so please correct any glaring errors in my understanding. I am an architecture researcher at Penn State working on Processing in Memory (PIM) architectures. Currently, I plan to use LLVM to detect and replace groups of instructions which can be accelerated in memory. Once a group of
2017 Oct 03
2
invalid code generated on Windows x86_64 using skylake-specific features
I figured it out. I was using this implementation of __chkstk from compiler-rt: DEFINE_COMPILERRT_FUNCTION(___chkstk) push %rcx cmp $0x1000,%rax lea 16(%rsp),%rcx // rsp before calling this routine -> rcx jb 1f 2: sub $0x1000,%rcx test %rcx,(%rcx) sub $0x1000,%rax cmp $0x1000,%rax ja 2b 1:
2017 Dec 11
2
New x86 instruction with opcode 0x0F 0x7A
Hi all, I'm trying to simulate an extended x86 architecture on gem5 with several new instructions. My hardware setup is done and now I'd like llvm to accept the existence of the new instruction passed in inline assembly and output the correct opcode and registers. I chose the two-byte opcode 0x0F 0x7A and I would like the instruction to have the same operands and return values as CVTPS2PI
2018 Mar 28
1
Taking over an x86 opcode for my own instruction
tl;dr, I'd like to add my own instruction, but I'm running into problems due to my lack of x86 encoding/decoding understanding. Hello all. Currently, I'm working on adding my own x86 instruction. I have done this once before; the basic process I used was: 1. Find an unused opcode, e.g. 0xF1 in this table: http://ref.x86asm.net/coder32.html 2. Insert an instruction into
2012 Nov 20
4
[LLVMdev] Question about compiling LLVM through cross-compiler for ARM
Hi All, I'm trying to compile clang+llvm on my desktop with cross-compiler to be able to work with llvm commands in ubuntu-arm image whithin gem5. If anybody has done this before I'd be so thankful to know the exact process and commands. I tried to configure llvm as follows but I couldn't get the arm-arm version correctly. To sum up, I need to cross-compile llvm for ARM to work in
2006 Oct 01
2
[LLVMdev] Instruction descriptions question
Hi, I'm trying to implement a new backend for an embedded CISC processor. Therefore I thought that it makes sense to take X86 target as a basis, to save some time. But when I look into the X86InstrInfo.td, I have a very strong feeling that it is one of the most complex instruction set descriptions compared to other targets. I can imagine that this is due to the complexity of X86's
2015 Mar 11
5
[LLVMdev] Customize Standard C Library Using LLVM (to support llvm backend optimization)
Purpose: I implemented a pass on LLVM backend that changes the output format of *ARM* assembly/binary (e.g add a jump at the end of each basic block to eliminate fall through). By calling: llc -march=arm somefile.bc it generates expected arm assembly/binary that runs properly on arm gnu linux (I use qemu-arm and gem5 to simulate it). Now I want to do the same thing on standard c library, but
2013 Mar 11
0
[LLVMdev] Running cross compiled binaries for ARM on gem5
Hi Silky, If I got correctly, you seem to be trying to run a bare-metal image on your model, but you compile with linux-gnueabi GCC. I don't know if that will make a difference, but I'd try to use none-eabi GCC toolchain and set the -target armv7a-none-eabi just in case. On 10 March 2013 00:26, Silky Arora <silkyar at umich.edu> wrote: > Most of the search results talk about