similar to: [PTX Backend] Current optimizations for Memory Load Instructions?

On Sun, May 8, 2011 at 2:41 AM, 陳韋任 <chenwj at iis.sinica.edu.tw> wrote: > Hi, all > > I am trying to add "not" instruction support to PTX backend. > I add the line below in PTXInstrInfo.td, > > defm NOT : PTX_LOGIC<"not", not>; > > But I get errors below, > > >

Hi, Hope you've got this to work. LLVM IR is pretty low-level, much more so than PTX. As there are quite a few different ways to achieve the same thing in PTX, it's likely that we won't need to handle all of the different instructions for PTX as the IR will only support a subset of them. In the future, I would suggest putting together the test case first and only when the backend

Hi, all I am trying to add "not" instruction support to PTX backend. I add the line below in PTXInstrInfo.td, defm NOT : PTX_LOGIC<"not", not>; But I get errors below, ------------------------------------------------------------------------------- Included from PTX.td:75: PTXInstrInfo.td:732:10: error: Value 'PTX_LOGIC::opnode' of type 'SDNode' is

Hi, Dan I add "not" instruction support in PTXInstrInfo.td as you suggested before. multiclass PTX_LOGIC_2OP<string opcstr,PatFrag opnode> { ... } Now I am trying to write test case for logic and shift operations. But I have a trouble in mapping LLVM IR to PTX IR for "not" instruction. The test case I wrote is, define ptx_device i16 @t4_u16(i16 %x) { ; CHECK:

Hi all, Does PTX backend support llvm sitofp instruction? I failed to compile my llvm source when use llc -march=ptx32. The reason is that the source has a sitofp instruction. After i changed the instruction into uitofp manually, it passed. Thanks in advance, best, Yabin -------------- next part -------------- An HTML attachment was scrubbed... URL:

> Though, I have to agree with Dan on assessing whether the selection logic is > needed. Do you have an example where the PTX back-end cannot generate code > for some piece of LLVM IR because of the lack of 'not' selection? Honestly, I don't have such example yet. Just want to try to implement some instructions by myself. :p Regards, chenwj -- Wei-Ren Chen (陳韋任)

On Thu, May 12, 2011 at 9:56 PM, 陳韋任 <chenwj at iis.sinica.edu.tw> wrote: > Hi, Dan > > Someone on the irc suggest me using custom lowering to do the mapping > correctly. But I am still trying to figure out how to do that. > Custom lowering means implementing the SelectionDAG instruction selection in the C++ class instead of the TableGen file. See PTXISelLowering.{h,cpp}

> Does PTX backend support llvm sitofp instruction? Seems it doesn't support sitofp, search "Conversion to f32" in PTXInstrInfo.td. Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667

Hi! >>> Hi there, >>> >>> I have a working prototype of PTX backend, and I would like to >>> upstream it if possible. This backend is implemented by LLVM's target >>> independent code generator framework; I think this will make it easier >>> to maintain. >>> >> How does this relate, at all, to the backend here:

My implementation of predicated instructions is similar to ARM backend. I traced ARM and PowerPC backend for reference. If, David, you were saying a implementation of predication in LLVM IR, I didn't do that. It was partly because I was not (and is still not) very familiar with LLVM's design; so I didn't know how to do that. I agree what Micah said; LLVM's code generator has a

> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of David A. Greene > Sent: Tuesday, August 10, 2010 12:05 PM > To: Helge Rhodin > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] PTX backend, BSD license > > Helge Rhodin <helge.rhodin at alice-dsl.net> writes: > > >> But I

Thanks David for the comments. Sorry for the late reply. On Mon, Aug 23, 2010 at 11:52 PM, David A. Greene <greened at obbligato.org> wrote: > Che-Liang Chiou <clchiou at gmail.com> writes: > >> Hi there, >> >> Thank Nick for kindly reviewing the patch.  Here is the link to the >> source code of the PTX backend; it would help Nick review the patch.

Che-Liang Chiou <clchiou at gmail.com> writes: > I surfed their code, and it seems that they didn't use code generator. > That means there design should be similar to CBackend or CPPBackend. > So I guess it can't generate some machine instructions like MAD, > and there are some PTX instruction set features that are hard to exploit > if not using code generator. >

Looking further during down time at the dev meeting today, it actually seems that PTX atom.* and red.* intrinsics map extremely naturally onto the LLVM atomicrmw and cmpxchg instructions. The biggest issue is that a subset of things expressible with these LLVM instructions do not trivially map to PTX, and the range of things naturally supported depends on the features of a given target. With

From what I can tell, the truncstore paths all fail instruction selection in the current PTX backend. This is easy to work around for int types >= 16 bits by setting the truncstore action to expand in PTXISelLowering.cpp, but this cannot handle i8 values, since the PTX backend has no register representation for i8s. As a result of all this, it is not possible to store to i8 pointers at all.

Che-Liang Chiou <clchiou at gmail.com> writes: > Hi there, > > I have a working prototype of PTX backend, and I would like to > upstream it if possible. This backend is implemented by LLVM's target > independent code generator framework; I think this will make it easier > to maintain. How does this relate, at all, to the backend here:

On Fri, Aug 6, 2010 at 6:47 PM, Che-Liang Chiou <clchiou at gmail.com> wrote: > Hi there, > > I have a working prototype of PTX backend, and I would like to > upstream it if possible.  This backend is implemented by LLVM's target > independent code generator framework; I think this will make it easier > to maintain. > > I have tested this backend to translate a

Hi there, Thank Nick for kindly reviewing the patch. Here is the link to the source code of the PTX backend; it would help Nick review the patch. http://lime.csie.ntu.edu.tw/~clchiou/llvm-ptx-backend.tar.gz The source code from above link is a working prototype. So it will not be upstreamed as is; I will refactor and add unimplemented features while upstreaming it. That said, the source code

Hi everybody, I am trying to produce ptx code starting from OpenCL C. I am experiencing a problem concerning pointer parameters. Here follows an example: kernel void function(__global float* parameter1) {} NVIDIA NVCC Compiler: .entry function( .param .u32 *.ptr* .global .align 4 function_param_0 ) { ret; } CLANG + LLVM PTX backend // (skipping builtin functions definitions) .entry

Hi, The PTX backend we developed (CBackend approach, does not use the target independent code generator) is already more advanced. An older version is published here: http://sourceforge.net/projects/llvmptxbackend/ We recently eliminated a bug which increased the number of required registers per thread. Surprisingly, without that bug the generated code is already comparable to code generated