similar to: [cfe-dev] Disabling vectorisation at '-O3'

No, I’m wrong. I think that bug is actually in ‘hasFlag’ itself. In ‘llvm/lib/Option/ArgList.cpp’ line #70: bool ArgList::hasFlag(OptSpecifier Pos, OptSpecifier PosAlias, OptSpecifier Neg, bool Default) const { if (Arg *A = getLastArg(Pos, PosAlias, Neg)) return A->getOption().matches(Pos) || A->getOption().matches(PosAlias); return

Yes, it looks like passing ‘EnableVec’ and ‘EnableSLPVec’ to ‘Args.hasFlag’ should be replaced with ‘false’ and then it has the expected behaviour. MartinO From: cfe-dev [mailto:cfe-dev-bounces at lists.llvm.org] On Behalf Of Martin J. O'Riordan via cfe-dev Sent: 01 March 2018 18:02 To: 'Richard Smith' <richard at metafoo.co.uk> Cc: 'Clang Dev'

I've come across a need to know whether an option was set true, false or unspecified. If it is true I want to do one thing, if it is false I want to do something else and if it is unspecified I want to do nothing. ArgList::hasFlag is a convenient way to check true/false with a default value. An ArgList::hasFlag that returned Optional<bool> would allow checking the unspecified case.

There's always the hypothetical template<typename T> llvm::Triple giveMeATripleDamnYou(const T &); Just keep adding implementations until you stop needing to. ;-) Cheers. Tim. On 1 January 2018 at 17:00, Martin J. O'Riordan <MartinO at theheart.ie> wrote: > Thanks Tim, > > Sometimes my hacks last longer than I want as it isn't always apparent how I can

Thanks for reporting this. Looks like this one was missed -- the declaration should have been #ifdef'd away along with the definition. A quick grep indicates there are a number of them that need to be fixed. Here's the original commit: commit 88d207542b618ca6054b24491ddd67f8ca397540 Author: Matthias Braun <matze at braunis.de> Date: Sat Jan 28 02:02:38 2017 +0000 Cleanup

We'll be doing something similar for our OpenVMS port.  Right now I'm using "AsmStreamer->GetCommentOS()" and writing to the stream at the assembler level but that gets aligned on a right-side column (the column is hardcoded) and you have to be in verbose mode.  So if you come up with something or have a quick design, post it so perhaps we can leverage each other's work. 

Martin: It sounds like you are doing is more akin to shuffle selection than fusion and therefore it's a better fit for instruction selection than DAGCombining. Try movign it to <Target>ISelDAGToDAG's Select (or potentially PreprocessISelDAG). Th -Nirav On Tue, Mar 6, 2018 at 4:05 PM Martin J. O'Riordan <MartinO at theheart.ie> wrote: > We discovered what is

Hi Martin On 25 September 2017 at 21:13, Martin J. O'Riordan <MartinO at theheart.ie> wrote: > Yes, if it is in the interface it would make more sense to have a null implementation at the very least. In my out-of-tree target, I also removed them from the interface if the build was for Release to ensure that I got compile-time errors to reveal other places I might have otherwise

Yes, if it is in the interface it would make more sense to have a null implementation at the very least. In my out-of-tree target, I also removed them from the interface if the build was for Release to ensure that I got compile-time errors to reveal other places I might have otherwise missed. All the best, MartinO -----Original Message----- From: Dibyendu Majumdar [mailto:mobile at

Thanks very much Eric for taking the time to carefully explain this to me. So if I am the author of the backend for a new processor technology, or willing to modernise my existing implementation, you would recommend that the ‘-mcpu’ option is deprecated and probably best not used at all, or perhaps just as a synonym for ‘-march + -mtune’? The first part of the target triple guides the

Cool this is better than I expected - I never thought about the YAML support. And the document reference is really very good. Thanks Francis, MartinO -----Original Message----- From: Francis Visoiu Mistrih [mailto:francisvm at yahoo.com] Sent: 05 February 2018 21:43 To: Martin J. O'Riordan <MartinO at theheart.ie> Cc: LLVM Developers <llvm-dev at lists.llvm.org>; Adam Nemet

Hi David, When I use CMake to configure, ‘zlib’ and its header are detected - I build on CentOS 6.5 or CentOS 7. Since I run CMake from the command-line, I tried added ‘-DLLVM_ENABLE_ZLIB=0’ and ‘-DLLVM_ENABLE_ZLIB=1’ (using ‘-DLLVM_ENABLE_ZLIB=ON’ does not seem to work). Both ‘clang’ and ‘llvm-profdata’ (and all other tools and utilities) are configured and built together, in any event,

Thanks Tim, Sometimes my hacks last longer than I want as it isn't always apparent how I can implement it properly. At the moment I am looking at changes I need to 'MachineBasicBlock::ReplaceUsesOfBlockWith'. It is most likely that I need to handle the issue in a different way, but the change I need works here for my target for the time being, but breaks X86 which I also build for

Thanks Matthias, I have both a pre-RA and a post-RA scheduler, and I had thought that I could track “has RA happened?” by setting a flag in my pre-RA scheduler as it completes - my suspicion (which you have confirmed) was that “#vregs == 0” was not a safe assumption. What I cannot be sure of, is what passes execute after my pre-RA scheduler but before RA, and what passes execute after RA but

Hi Martin, On Fri, 3 Aug 2018 at 14:10, Martin J. O'Riordan <MartinO at theheart.ie> wrote: > $ git branch --list > * master > martino By default "git branch" only lists local branches. "git branch -a" will list all of them, including (for me) "remotes/origin/release_70". If you just type "git checkout release_70" git will

> On Jan 16, 2018, at 11:31 PM, Martin J. O'Riordan <MartinO at theheart.ie> wrote: > > Thanks Matthias, > > I have both a pre-RA and a post-RA scheduler, and I had thought that I could track “has RA happened?” by setting a flag in my pre-RA scheduler as it completes - my suspicion (which you have confirmed) was that “#vregs == 0” was not a safe assumption. What I

Hi Martin, I think this is another example of why we might consider having such function level attributes.. yes.  Chad On 4/4/2018 11:42 AM, Martin J. O'Riordan via llvm-dev wrote: > > Sorry, my reply “to all” left out LLVM-Dev > > *From:*Martin J. O'Riordan [mailto:MartinO at theheart.ie] > *Sent:* 04 April 2018 16:41 > *To:* 'David Blaikie' <dblaikie at

We discovered what is happening. SDAGCombiner essentially looks at various combinations of nodes to do with vectors, and when it can, it creates a vector shuffle. The problem is, that our vector shuffle lowering builds new trees with vector element, or vector sub-vector insert sequences. The generic DAGCombiner, reconstructs these into a new shuffle, and so the loop continues - we reduce it,

Hi Serge, Thanks for your help. I have looked at the change log, and so far as I can tell, my implementation is pretty much identical to all of the in-tree targets, but I’m missing something and can’t see what it is. I have simplified my TD description to just: def MyCallseqStart : SDNode<"ISD::CALLSEQ_START", SDCallSeqStart<[SDTCisVT<0, i32>,

On Tue, Jan 16, 2018 at 11:13 PM, Martin J. O'Riordan <MartinO at theheart.ie> wrote: > Hi Sean, > > > > I had to add ‘v16f16’ to our out-of-tree target, and this was to > primarily to allow me to express lowering for all the OpenCL types (well, > except for the ‘v3T’ types). > > > > The trend does seem to be towards larger bit-width SIMD registers, and