similar to: Source level code transformation V.S. IR-level code transformation

2018-01-15 9:36 GMT+08:00 Linchuan Chen via llvm-dev < llvm-dev at lists.llvm.org>: > Dear all, > I'm working on a simple code transformation problem that can be > described as below: > > for a C++ loop: > > *for (int i = 0; i < N; ++i) {* > * a = M[i] + b;* > * }* > > I want to transform it to: > > *int A[4]; *

Thanks Weiren! My goal is to transform the code automatically by doing some code analysis, instead of rewriting it manually. To do this source level auto transformation, do you have any suggestions on what tool to use? Thanks again!! On Mon, Jan 15, 2018 at 04:25 陳韋任 via llvm-dev <llvm-dev at lists.llvm.org> wrote: > 2018-01-15 9:36 GMT+08:00 Linchuan Chen via llvm-dev <

Thanks Amara so much for the info! One more question: what do people usually do if they want to generate vectorized code for some existing c/c++ code? Do they usually do C/C++ source level transformation, or do at LLVM's IR level? I know clang supports auto vectorizations, such as loop vectorization and SLP, but they are not flexible enough if we want to do more custom vectorizations or

> On 8 Jan 2018, at 19:41, Linchuan Chen <chenlinc at cse.ohio-state.edu> wrote: > > Thanks Amara so much for the info! > > One more question: what do people usually do if they want to generate vectorized code for some existing c/c++ code? > Do they usually do C/C++ source level transformation, or do at LLVM's IR level? > > I know clang supports auto

Hi everyone, I'm quite new to LLVM, but am working on a project that might need to generate some SIMD code using LLVM. The SIMD code will be using INTEL MIC intrinsics and I'm not sure about the steps and tool set that I need to use to generate those. I also have a confusion on the following problems: 1. Do people usually generate SIMD code at source code level, using __m512?

> On 6 Jan 2018, at 00:26, Linchuan Chen via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi everyone, > > I'm quite new to LLVM, but am working on a project that might need to generate some SIMD code using LLVM. The SIMD code will be using INTEL MIC intrinsics and I'm not sure about the > steps and tool set that I need to use to generate those. > > I

Hi weiren, Thanks for your suggestion! Yes, I am trying to do this "nested flattening". It seems that I need a post-dominator tree-based algorithm to flatten the nested loops from the innermost to the outermost, level by level. Is there any feature already existed in LLVM tools? Or similar? On Sun, Oct 22, 2017 at 2:31 AM, 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw> wrote: > If

Thanks Amara very much! I will take a look! On Mon, Jan 8, 2018 at 12:01 PM, Amara Emerson via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 8 Jan 2018, at 19:41, Linchuan Chen <chenlinc at cse.ohio-state.edu> > wrote: > > Thanks Amara so much for the info! > > One more question: what do people usually do if they want to generate > vectorized code for some

>> What needs to be done (on a high level) in order to have the auto vectorizer succeed on the test function as given erlier? > Maybe you could rewrite the loop in a way that will expose contiguous memory accesses. Is this something you could do ? > Hi Nadav, the only option I see is to unroll the loop by hand. Since the array access is consecutive over 4 loop iterations I gave it a

On Oct 30, 2013, at 6:10 PM, Frank Winter <fwinter at jlab.org> wrote: > the only option I see is to unroll the loop by hand. Since the array access is consecutive over 4 loop iterations I gave it a try and unrolled the loop by a factor of 4. Which gives the following array accesses: > > loop iter 0: > index_0 = 0 index_1 = 4 > index_0 = 1 index_1 = 5 > index_0 = 2

Hi Frank, > We are looking at a variety of target architectures. Ultimately we aim to run on BG/Q and Intel Xeon Phi (native). However, running on those architectures with the LLVM technology is planned in some future. As a first step we would target vanilla x86 with SSE/AVX 128/256 as a proof-of-concept. Great! It should be easy to support these targets. When you said wide-vectors I assumed

> 2.i want to write such a test:translate a *.ll(i.e:hello.ll) file to a > *.c file(i.e:hello.c) with llc,then verify if the .c file contian a > certain string(i.e:"abc:). so: It seems you want to test LLVM C backend, go looking for llvm-3.0.src/test/CodeGen/CBackend/* (C backend had been removed from LLVM 3.1). HTH, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute

Hi everyone, I hope to implement a feature to transform an IR with "while" or "for" loops to a new IR with no loop. Instead, I just want to use if-else statements in the new IR to implement the original semantics. I can easily write a transform pass to handle the 1-level loop case, but for nested loops it seems a little harder. Can you show me some hints? Thank you very

Hi all, The slides we used on "CGO MCLinker and LLVM Tutorial" are now available on the MCLinker website: http://code.google.com/p/mclinker/wiki/2013CGOTutorial Enjoy! - The CGO Tutorial on MCLinker and LLVM 2013 committee

Hi, I've been playing around with the SLPVectorizer trying to get it to vectorize this simple program: define void @vector(i32 addrspace(1)* %out, i32 %index) { entry: %0 = alloca [4 x i32] %x = getelementptr [4 x i32]* %0, i32 0, i32 0 %y = getelementptr [4 x i32]* %0, i32 0, i32 1 %z = getelementptr [4 x i32]* %0, i32 0, i32 2 %w = getelementptr [4 x i32]* %0, i32 0, i32 3

Hi Tom, Thanks for working on this. The SLP-vectorizer thinks that %X %Y %Z and %W alias, so it tries to perform 4 scalar store operations (which is a bad idea). We need to figure out why AA thinks that X and Y may alias. Maybe there is a problem with the code that uses AA. Thanks, Nadav On Oct 24, 2013, at 2:04 PM, Tom Stellard <tom at stellard.net> wrote: > Hi, > >

Hello, We would like to propose making LoopVectorize aware of SLP operations, to improve the generated code for loops operating on struct fields or doing complex math. At the moment, LoopVectorize uses interleaving to vectorize loops that operate on values loaded/stored from consecutive addresses: vector loads/stores are generated to combine consecutive loads/stores and then shufflevector

Hi, I have come across a major regression resulting after SLP vectorization (+18% on SystemZ, just for enabling SLP). This all relates to one particular very hot loop. Scalar code: %conv252 = zext i16 %110 to i64 %conv254 = zext i16 %111 to i64 %sub255 = sub nsw i64 %conv252, %conv254 ... repeated SLP output: %101 = zext <16 x i16> %100 to <16 x i64> %104 = zext

Hi Florian! This proposal sounds pretty exciting! Integrating SLP-aware loop vectorization (or the other way around) and SLP into the VPlan framework is definitely aligned with the long term vision and we would prefer this approach to the LoopReroll and InstCombine alternatives that you mentioned. We prefer a generic implementation that can handle complicated cases to something ad-hoc for some

----- Original Message ----- > > Hi Nadav, > > that's the whole point of it. I can't in general make the index > calculation simpler. The example given is the simplest non-trivial > index function that is needed. It might well be that it's that > simple that the index calculation in this case can be thrown aways > altogether and - as you say - be replaced by