similar to: How to get started with instruction scheduling? Advice needed.

On Mon, Jun 21, 2010 at 1:12 AM, Javed Absar <javed.absar at gmail.com> wrote: > Hi Tobias: > > Thanks for replying . So if I understand correctly,  in LLVM currently, the > Polyhedral model is being built ( LLVM IR -------> Poly Model ----------> > LLVM IR ). > This is for compile-time optimizations of loop-nests [e.g. > loop-transformations to expose parallelism

Hi Reid, Unfortunately yes, it is. > If we do go with approach 3, I'd recommend adding a single metadata attachment that controls all sections a global could possibly live in (text, data, rdata, bss). I agree with this, although I think using metadata here wouldn't be right - don't we need to use attributes when dropping metadata would cause miscompiles? I was considering adding

Hi all, Can anyone tell me the current state of instruction scheduling in LLVM, i.e. what all internal scheduling algorithms and whether constraint solving methods are used in LLVM for a single issue processor ? Please let me know if anyone has any information about it. Thanks, Siddharth -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Mon, Jun 21, 2010 at 10:27 AM, Daniel Berlin <dberlin at dberlin.org> wrote: > On Mon, Jun 21, 2010 at 1:12 AM, Javed Absar <javed.absar at gmail.com> wrote: >> Hi Tobias: >> >> Thanks for replying . So if I understand correctly,  in LLVM currently, the >> Polyhedral model is being built ( LLVM IR -------> Poly Model ----------> >> LLVM IR ).

Javed, I'd like to add that, mostly through Tobi's efforts, we were able to have isl (the integer set library) on which Polly depends relicensed such that it is now distributed under the MIT license, and thus Polly should be eligible for inclusion as some of LLVM's core analysis and transformation passes. -Hal ----- Original Message ----- > From: "Javed Absar"

Hi Javed, Developing a good loop vectorizer takes several years. The work on the GCC vectorizer began in 2004, and they spent several years improving and optimizing their vectorizer. They started by vectorizing simple loops, and added features that they needed in order to vectorize additional loops that were important for them. They started with a single-block loops, and later they added

So if I use the SchedMachineModel method, can I just skip itineraries? Phil On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Target does make a difference. VLIW needs more hand-holding. For what you > are describing it should be fairly simple. > > > > Best strategy – see what other targets do. ARM might be a good start for > generic

Javed Absar wrote: > Hi > > I read on LLVM blog that meta-data has been implemented to coney debug > information to run-time system. > Can one use meta-data to convey developer specifc hints to run-time > system (e.g. JIT compiler)? > Keen to know your thoughts on this. I don't see why not. I've used LLVM metadata to record type-inference information and to

Hi Tobias: Thanks for replying . So if I understand correctly, in LLVM currently, the Polyhedral model is being built ( LLVM IR -------> Poly Model ----------> LLVM IR ). This is for compile-time optimizations of loop-nests [e.g. loop-transformations to expose parallelism or improve locality etc]. Yes, thats great for optimizing loop-nests. As an additional, since the real value of LLVM

Hi Javed, On 06/18/10 14:07, Javed Absar wrote: > Hi: > I worked on loop-optimizations techniques previously using ORC. > Currently i see lots of research on speculative parallelization of > loops ... specially because multicores [for embedded systems] is > becoming popular. In other words, because you have > multiple cores, you can start some loops [Fast-Track] as if there is

Thanks Reid/Jonathon for your replies. Reid, An important case against module level flags is that it wont allow changing or resetting section names e.g. int a; #pragma clang section bss = "xyz" int b; In case above, users would like to see only 'b' placed in 'xyz' and not 'a' as well. Link pointed to by Jonathon seems to require same behavior.

It would be great to get "accurate" dependence analysis from polyhedral framework. Anyone working on making polly into analysis+Transforms framework? -Prashantha -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Sahasrabuddhe, Sameer Sent: Monday, October 08, 2012 9:03 AM To: Hal Finkel; Javed Absar Cc: llvmdev at

Hi all, I am proposing the integration of a backend targeting the RISC-V ISA. RISC-V is a free and open instruction set architecture that was originally developed at UC Berkeley. Future development of the ISA specification will be handled by the 501(c)(6) non-profit RISC-V Foundation and its members <https://riscv.org/membership/?action=viewlistings>. You can find much more information at

> On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using itineraries over the per operand scheduling. > > I

On 06/21/10 07:12, Javed Absar wrote: > Hi Tobias: > Thanks for replying . So if I understand correctly, in LLVM currently, > the Polyhedral model is being built ( LLVM IR -------> Poly Model > ----------> LLVM IR ). > This is for compile-time optimizations of loop-nests [e.g. > loop-transformations to expose parallelism or improve locality etc]. > Yes, thats great for

Hi Phil. You more or less answered your own question, but let me give you some more info. Maybe it is of use. >From what I understand the SchedMachineModel is the future, although it is not as powerful as itineraries at present. The mi-scheduler is mostly developed around out-of-orders cores, I believe (I love to hear arguments on the contrary). Some of the constraints that can be found in

Hi, yesterday I was trying to create local mirror of CentOS7 using katello/pulp. I was receiving CRC checksum errors while attempting to sync the mirror. The particular error in question was: Feb 12 07:46:34 bazinga pulp: pulp_rpm.plugins.importers.yum.sync:INFO: [e2cd9930] Generating metadata databases. Feb 12 07:47:06 bazinga pulp: pulp_rpm.plugins.importers.yum.sync:ERROR: [e2cd9930]

Hello. Hal, the problem I have is that it doesn't advance at the next available instruction - it always gets the same store. This might be because I did not specify in a file like [Target]Schedule.td the functional units, processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the

+llvm-dev properly this time. On Fri, 10 Mar 2017 at 09:42 James Molloy <james at jamesmolloy.co.uk> wrote: > Hi Reid, all, > > +llvm-dev as this RFC involves changes in Clang and LLVM. > > This RFC has stagnated and I think that's partially because the proposal > isn't particularly elegant and is light on details. We've been having a > rethink and have a

Hi Nadav (and others who are related to this issue) - I saw some discussions on loop vectorizer that you are planning to write. Do you foresee using Polyhedral Framework (polly project) in some way in that. Thanks J. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121007/476abc1c/attachment.html>